Aritra Sengupta Man Cao Michael D. Bond and Milind Kulkarni

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Presentation transcript:

Aritra Sengupta Man Cao Michael D. Bond and Milind Kulkarni Legato: Bounded Region Serializability Using Commodity Hardware Transactional Memory Aritra Sengupta Man Cao Michael D. Bond and Milind Kulkarni

Programming Language Semantics? Data Races C++ no guarantee of semantics – “catch-fire” semantics Java provides weak semantics Posing a huge problem for programmers

Weak Semantics Data data = null; boolean done= false; data = new Data(); done = true; if (done) data.foo(); This is a Java program.

Null Pointer Exception Weak Semantics Data data = null; boolean done= false; T1 T2 data = new Data(); done = true; if (done) data.foo(); This is a Java program. Null Pointer Exception

Null Pointer Exception Weak Semantics Data data = null; boolean done= false; T1 T2 data = new Data(); done = true; if (done) data.foo(); Null Pointer Exception This is a Java program. No data dependence: Reordering effect

Need for Stronger Memory Models “The inability to define reasonable semantics for programs with data races is not just a theoretical shortcoming, but a fundamental hole in the foundation of our languages and systems…” Give better semantics to programs with data races Stronger memory models – Adve and Boehm, CACM, 2010 Main problem with strong memory models have high overhead

End-to-End Memory Models: Run-time cost vs Strength (Unbounded) Synchronization-free Region Serializability Run-time cost Bounded Region Serializability SC DRF0 (C++/Java) Strength

End-to-End Memory Models: Run-time cost vs Strength (Unbounded) Synchronization-free Region Serializability Run-time cost Dynamically Bounded Region Serializability via EnfoRSer1 SC DRF0 (C++/Java) Strength 1. Sengupta et al. Hybrid Static-Dynamic Analysis for Statically Bounded Region Serializability. ASPLOS, 2015.

Dynamically Bounded Region Serializability (DBRS) acq(lock) methodCall() Regions are bounded statically and dynamically rel(lock)

Dynamically Bounded Region Serializability Eliminates SC violation Eliminates some atomicity violations SC+Atomicity of bounded regions1 DRF0 SC DBRS hsqldb6 Infinite loop Correct sunflow9 Null pointer exception jbb2000 Corrupt output sor lufact moldyn raytracer Fails validation 1. Sengupta et al. Hybrid Static-Dynamic Analysis for Statically Bounded Region Serializability. ASPLOS, 2015.

Benchmarks: DaCapo 2006, 2009 and SPECjbb benchmarks Intel Xeon with TSX. A 14-core processor 1. Sengupta et al. Hybrid Static-Dynamic Analysis for Statically Bounded Region Serializability. ASPLOS, 2015.

End-to-End Memory Models: Run-time cost vs Strength (Unbounded) Synchronization-free Region Serializability Run-time cost Dynamically Bounded Region Serializability via EnfoRSer SC This work: HTM-based dynamically bounded region serializability DRF0 (C++/Java) Strength

Outline Challenges Naïve implementation with hardware transactional memory Limitations of using HTM for DBRS Approach Overcoming limitations Our approach to DBRS enforcement: Legato Evaluation Main problem with strong memory models have high overhead

Enforcing DBRS with Commodity Hardware Transactional Memory (HTM) Transaction start Transaction End

Enforcing DBRS with Commodity Hardware Transactional Memory (HTM) Transaction Start Transaction End Transaction Start Transaction End

Enforcing DBRS with Commodity Hardware Transactional Memory (HTM) Transaction Start Transaction End Transaction Start Transaction End

High cost of TSX instructions Start/End ≈ three atomic operations!2 2. Yoo et al. Performance Evaluation of Intel TSX for High-Performance Computing, SC 2013

Legato: Key Idea Merge several regions into a single transaction: amortize the cost of starting and stopping a transaction

Legato: Key Idea Transaction Start Transaction End Transaction Start

Legato: Key Idea Transaction Start Transaction Merge

Legato: Key Idea Transaction Start Transaction Merge Transaction Merge

Legato: Key Idea Transaction End Transaction Start Transaction Merge

Challenges Conflicts abort transactions: wasted work Capacity aborts: larger transactions have larger footprint, unknown a priori HTM-unfriendly operations: hardware interrupts, page faults etc.

Per-transaction cost vs Abort cost Transaction Abort Transaction Start Transaction Merge Transaction Merge

Per-transaction cost vs Abort cost Transient cause: conflicts, hardware interrupts => Retry transaction Capacity abort: end before culprit region Start new transaction Transaction Abort Transaction Start Transaction Merge Transaction Merge

Per-transaction cost vs Abort cost Transaction Abort Transaction Start Transaction Merge Transaction Merge

Per-transaction cost vs Abort cost Transient cause: conflicts, hardware interrupts => Retry transaction Capacity abort: end before culprit region Start new transaction Transaction End Transaction Start Transaction Merge Transaction Merge

Per-transaction cost vs Abort cost Transient cause: conflicts, hardware interrupts => Retry transaction Capacity abort: end before culprit region Start new transaction Transaction End Transaction Start

Per-transaction cost vs Abort cost Transient cause: conflicts, hardware interrupts => Retry transaction Capacity abort: end before culprit region Start new transaction Unknown abort location Transaction Abort

Per-transaction cost vs Abort cost Transient cause: conflicts, hardware interrupts => Retry transaction Capacity abort: end before culprit region Start new transaction Transaction End

Per-transaction cost vs Abort cost Transient cause: conflicts, hardware interrupts => Retry transaction Capacity abort: end before culprit region Start new transaction Future transaction behavior unknown Minimal Learning Transaction End

Legato: Our Approach Decide on a merge target: use history of previous transaction 1. Temporary target changes rapidly: capture transient effects 2. Setpoint or “steady state” target changes slowly: capture program phases

Merging Algorithm Curr Target: 8 Setpoint: 8

Merging Algorithm: Initial Phase Curr Target: 8 Setpoint: 8 Transaction Start

Merging Algorithm: Initial Phase Curr Target: 8 Setpoint: 8 Transaction Merge

Merging Algorithm: Initial Phase Curr Target: 8 Setpoint: 8 Transaction Merge

Merging Algorithm: Recover from Transient Error Curr Target: 8/2 = 4 Setpoint: 8 Rapid action:

Merging Algorithm: Recover from Transient Error Curr Target: 4 Setpoint: 8 Transaction Start

Merging Algorithm: Recover from Transient Error Curr Target: 4 Setpoint: 8 Transaction Merge

Merging Algorithm: Recover from Transient Error Curr Target: 4/2 = 2 Setpoint: 8

Merging Algorithm: Recover from Transient Error Curr Target: 2 Setpoint: 8 Transaction Start

Merging Algorithm: Recover from Transient Error Curr Target: 2 Setpoint: 8 No Action: Skeptical Transaction End

Merging Algorithm: Build up to Setpoint Curr Target: 2*2 = 4 Setpoint: 8 Transaction End

Merging Algorithm: Build up to Setpoint Curr Target: 4*2 = 8 Setpoint: 8 Aggressive Transaction End

Merging Algorithm: Change of Program Phase Curr Target: 9 Setpoint: 8 + 1 = 9 Transaction End

Merging Algorithm: Change of Program Phase Curr Target: 9 Setpoint: 8 + 1 = 9 Transaction End Enter a low-conflict program phase => more aggressive merging

Merging Algorithm: Change of Program Phase Curr Target: 10 Setpoint: 9 + 1 = 10 Transaction End

Implementation and Evaluation

Implementation Developed in Jikes RVM 3.1.3 Code publicly available in Jikes RVM Research Archive

Run-time Performance

Run-time Performance

Run-time Performance

Run-time Performance

Run-time Performance More stable overhead

JIT Compilation Time

JIT Compilation Time

JIT Compilation Time 1.45

JIT Compilation Time 1.45 Complex compiler transformations Simple instrumentation

Related Work Checks conflicts in bounded region DRFx, Marino et al., PLDI 2010 Checks conflicts in synchronization-free regions Conflict Exceptions, Lucia et al., ISCA 2010 Enforces atomicity of bounded regions BulkCompiler, Ahn et al., MICRO 2009 Atom-Aid, Lucia et al., ISCA 2008 Reducing dynamic misspeculations BlockChop, Mars and Kumar, ISCA 2012

Memory Models: Run-time cost vs Strength (Unbounded) Synchronization-free Region Serializability Run-time cost Dynamically Bounded Region Serializability via EnfoRSer1 SC Dynamically Bounded Region Serializability via Legato DRF0 (C++/Java) Strength 1. Sengupta et al. Hybrid Static-Dynamic Analysis for Statically Bounded Region Serializability. ASPLOS, 2015.