for Design Integration in Automotive Applications Jon Hancock, Dieter Metzner, Jürgen Schäfer, Chihao Xu Infineon Technologies AG, München / San Jose Outline: - System Simulation in the Design of Automotive Electronics - Modeling Methodology for Smart Power Switches - Model Validation - Conclusion A) Motivations, Situation at system development B) Method: Modular , hybrid (physics based <-> analog behavioural), mixed mode (analog<->digital) C) D) ... Power Semiconductors for Automotive Solutions

Trends in electrical system design for automotive applications: Reduced time-to-market and costs Increasingly complex and networked systems Design closer to critical values (e.g. thermal limits) > Therefore: System simulation, predominantly w. SABER System competence is required from suppliers Increased demand for behavioral models – accuracy + efficiency Crucial: overall costs including development > Customer benefits through use of behavioral models 3.) Often the real stress on the device is unknown to the designer potential reliability problems 4.) SABER <-> SPICE We see an increasing focus on request of SABER models rather than SPICE. (Especially in Europe, but also in USA) 5.) You know best

Integration of system simulation into the design flow Applications: Body- , Safety- and Power-Train-Electronics Areas: System Verification, Failure Modes, EMI Motivation: reduced development times by means of concept definition and verification, failure effects, avoiding redesigns Integration of Models into device- /ECU- specifications Car manufacturer -> ECU supplier -> component supplier Model specifications already exist SAE Standard to be released Preferred platform: presently SABER (MAST) Future: standardized HDL (e.g. VHDL-AMS !) Integration in design flow: In Europe only in pilot projects Semiconductor industry: standard since long (complexity) Model in specs: GM->Siemens VDO->Infineon (example) VW->Bosch-> Infineon SAE standard : How To specify models VHDL-AMS : open standard Hardware descr. Language. Acceptance in Europe will depend on availability of models. We will try to push it.... Main characterisitics: Mixed mode supported (Saber, PSPICE insufficient) Open Source Code (independent of simulators) all physical domains (mech, hydr. like SABER)

Potential Benefits: Behavioral Models as a new standard for specification of application specific devices Improved common understanding: a) Supplier -> Application: achieve solution concepts, acquire system know-how b) Customer -> Smart-Power-IC recognize potentials and limits of components Concept simulations for internal investigations (Top-Down Design for protection, dynamics, thermal aspects, EMC) Concept simulation: Can avoid redesigns, Top Down Method is lived, First Pilot BTS6166. (42V will be an interesting example)

Model Requirements/Challenges: - System simulation with complex loads, interfaces, sensors, etc - “Reasonable” CPU time consumption - All “important” system effects included Solution: Abstraction of functional blocks Concept: Separation into behavioral modules and physics-based device models My definition of what is reasonable (CPU time): the computation of results does not take much longer than their interpretation. What are important effects included.? Here you could reference to subsequent sections where some aspects become clear. Model requirements: sometimes specified by customer if not, maximum feature number: Timing, switching, losses, Temperature dependencies of important parameters, selfheating, avalanche, protection features, diagnosis, thermal model.....

Powertrain application using Multi-channel Low Side Switches Text Paper Fig.1 shows a typical application of the TLE6240GP, a 16-fold lowside switch designed for engine management applications: Comment: Here I don´t have to advice you what to say for pointing out what magnificient devices we offer.....

Functional structure of the TLE6240 with digital and analog blocks Physical design Text Paper: As shown in Fig. 2 this IC is a typical example of an application for a mixed mode analog/digital design. The analog power output channels are controlled partly by parallel analog input pins and partly by a serial digital input (Serial Parallel Interface, SPI). Internal Processing and serial output of error status signals is accomplished by digital circuitry, while power supply-, gate drive-, and sensing functions are analog. The features of the TLE6240 include: 16 low side channels 0.4 to 1.0 8 PWM channels (parallel input) and 8 channels controlled only by SPI overtemperature protection shortcircuit protection (current limitation) overvoltage protection status feedback via SPI (openload, shortcircuit, short to ground) The process used is a Infineon Smart Power Technology based on junction isolation, rated to 60 Volts Fig.3 illustrates the chip layout where the power output transistors (red stripes)can be well distinguished from the digital parts (center) of the circuit.

Repi Electro-thermal Compact Model of the Power MOS FET : Reduction of semiconductor equations with the aid of Finite Element Simulations => lumped model with all important physical effects Repi Text in paper To describe the Power MOS output transistor models accurately (correct switching transients and the on-state) In this case we are also using information of finite element software like Medici or Dessis to optimize the lumped element According to Fig. 5a, current paths and potential distributions in Silicon structures which result in nonlinear voltage controlled current sources. At this point all Parameters are derived from the basic equations of semiconductor physics. Comment: we see the current flow lines pinched in the channel and expanding in the drift region. This area (shape and extension) is dependent on vds and id , so the main challenge for the resistor description(Repi) is to account for that variing boundary conditions. Device Simulations are a valuable aid to identify meaningful simplifications Example of SPT -Technology (junction isolation)

Electro-thermal Compact Model of the Power MOS FET : - Nonlinear Characteristics of Channel and Drift Regions - Inverse Diode - Nonlinear Capacitances - Coupling of thermal and electrical equations Drain External Heatsink Gate Source Tj Tcase Tamb Rd (TJ ) Cth1 Cth2 Rth1 Rth6 Cth6 Vth (Tj ) Tepi me (Tj ) Comment: For the electrothermal interactions the concept of „average junction temperature“ is adopted. That means that no lateral effects like hot spots or current pinching are modeled. For the integral behaviour of the device at the pins this is o.k. as long as no unstable operation modes occur (negative differential resistance). However, in some cases (like here small SPT devices) SOA considerations can lead to too optimistic results.

Thermal Compact Models: Extraction of Lumped Model from 3D FEM Simulations Text in paper: The thermal behavior is normally described by the heat diffusion equation, a partial D.E. used to determine the transient cooling conditions of the power device. Because 3D heatflow is important (particularly in the case of a monolithic multichannel device), a lumped structure has to be built. To achieve the tradeoff between accuracy and complexity (for parameter extraction) a transient finite element simulation is performed which yields the thermal step response at the heat generating cells (self heating) and at the neighbouring influenced elements (cross-coupling). Then, a comprehensive lumped structure of the main heat paths is defined in a similar way to electrical RC networks, involving vertical and lateral components, still leaving the parameter values for each element undefined. With symbolic algebra software a closed form solution for the step responses can be calculated with arbitrary network parameters. At last, an optimizer with adequate constraints is used to find a reasonable combination of these parameters (Ri and Ci) which has the most similar transient response. Comment: This is an example of trilithic where the ideal method can be denonstrated more easily. In the TLE model in fact we used a geometric approach (parameters estimated by hand calculation, which were then adapted to measurements) The software used was an excel based FEM - Tool for calculation of step responses with integrated optimizer for parameter extraction (mathcad calculus->closed form solution)

Behavioral implementation of current limitation functional description and MAST - code In the current limiting concept an additional gate discharge path is turned on, if the measured current exceeds a specified value. The gate voltage is then limited by an analog feedback loop, thus shifting the output transistor to a lower curve Id=f(Vds).The implementation is done with a simple transconductance to discharge the MOS-gate. In addition, an interface to the digital world is needed for error processing: In the example of Fig. 6, the overcurrent flag ovlq is shown.In MAST, this functionality is implemented by the threshold function: Comment: Up to this point the problem was to reduce the partial diff. Equations f(x,y,z,t) to a set of ordinary Deqns f(t). Now we leave this physical domain to the transistor level design. The challenge: simplify hundreds of transistors to a few lines of code. Message:It´s not necessary to implement transistor by transistor of discharge paths and comparators. With a few lines of Code the main functionalities can be implemented The contribution iclim (gate discharge current for control of Idrain) is only evaluated (not equal zero) for the limiting case Thresholds are very effective for this purpose Iclim is added just like other state dependent current components at the gate node of the output transistor

Digital Modeling: behavioral MAST implementation of read-in process of the Serial Parallel Interface Paper Text: Serial input are entered into the input shift register when a logic low at the cs signal (chip select), a falling edge at the system clock and a logic high at the reset signal (Box 2) occur. The when section becomes active if one of this logic signals is changed (event-triggered). . .Figure 8 shows a simulation of one SPI cycle. The top signal is the system clock sclk, followed by chip-select csi and serial input si.The following signals d0_i - d15_i are the internal signals of the input shift register. As shown in the example the input shift register does not accept data before the second system clock pulse. Comment: Here you can point out that the MAST language doesn´t support vector assignments, which would be very helpful here (no more copy and paste of code lines). In general, MAST is not practical for large digital circuitry, nor does it work properly in all cases. I´m hoping these workarounds become obsolete with VHDL-AMS or Verilog AMS (Open Hardware description language for mixed signal) I decided that the timing discussed in the paper should be left out in the presentation (if you don´t object)

Model Validation (1) Example Short-Circuit-2: Verification of thermal model, gate drive and temperature sensor dynamics ! In general, a model specification should reflect typical datasheet values. Accordingly, all relevant datasheet features have to be validated. Fine-tuning of parameters is possible for adaption of the model to a particular device or in order to give a tighter correlation to characterization results. In Fig 9, the validation of the current limiting function and the thermal behavior is demonstrated by a ”short circuit2” operation mode: At t=2msec one channel is turned on with a load current of 0.8A which is slightly below the current limitation threshold (datasheet: 1.0A...2.0A). At t=4msec a short circuit occurs across the load terminals. After a short overshoot, the switch current is limited to 1.3A and the voltage at the output rises to the battery voltage level. The instantaneous power density at the ouput DMOS transistor is approximatively 400W/mm2 which heats the junction beyond the overtemperature protection level. So called thermal toggling is initiated, the protection function turns the DMOS off and on repetitively depending on the detected temperature level. Comment: This measurement reflects many internal effects (see heading of foil): initial current peak: ->gate drive, dmos output characteristics, sense delay.... Current limit: -> gate drive, dmos ,temperature Toggling frequency: -> Thermal model, T- sensor dynamics Meanwhile the decrease of current with self heating is simulated better than shown: Influenced by: alu-shunt-Tk, bipolar comparator characteristics Simulation Measurement Short circuit while turned on@25°C, Vbat=12V, 0.5A/div, 1msec/div

Model Validation (2) Switching Transients: R=6 Ohm, L=1H, Vbat=12V, Tcase=25°C Verification of MOS capacitances and gate drive characteristics Measurement 1A/div, 5V/div Simulation

Conclusion - with mixed mode, multi-domain behavioral models complete mechatronic systems can be simulated in reasonable CPU time - typical simulated problems: Dimensioning of components, critical operation modes, interaction between devices , conducted EMI - Redesigns can be avoided, bread-boarding reduced - Lifetime estimations based on experimental database - In future: focus on more complex IC´s (modular approach) behavioral models before first silicon simulation ready specifications of new ASSPs standardized HDL is very desirable - Free download of models on: www.infineon.com/simulate Comments: a) factor CPU time reduction : 500 compared to transistor level design b) EMI: effect of switching on line voltage , if: line impedances are modeled accurately sensitivity to line disturbances can be investigated , if gate drive and parsitic capacitances are included. C) Lifetime estimations: Temperature cycles can be characterized very well, all you need is an empiric relation: number of cycles = f(Tstart, delta T) This will become a literally „hot“ issue as soon as millions of applications are on the road with repetitive clamping and repetitive shortcircuit ! D) future: modular means module library for quick model development simulatable specifications: there are first examples like with bosch:“what could the device look like ?“ HDL: we plan a pilot project with VHDL-AMS (open platform)