CSCE 385: Computer Architecture Spring 2014 Dr. Mike Turi I/O

Processors/Memory Systems vs. I/O Systems Processor/Memory Systems – Emphasize performance and cost I/O Systems – Emphasize dependability and cost – Constrained by latency and bandwidth

Dependability, Reliability, and Availability Service failures and restorations MTTF – Mean time to failure MTTR – Mean time to repair Availability = MTTF / (MTTF + MTTR)

Improve MTTF Fault avoidance Fault tolerance Fault forecasting

Magnetic Disk Storage Platters Surfaces Tracks (concentric circles) Sectors Read/Write head – Cylinder – Seek

Flash Storage A type of EEPROM NOR flash – First type – Expensive NAND flash – Higher densities – Cheap – Block reads/writes Wearout and wear leveling

RAID Redundant Arrays of Inexpensive Disks RAID 0 (No Redundancy) – Striping RAID 1 (Mirroring) RAID 3-6 – Include use of parity

Busses Processor-Memory Bus – Short, high-speed I/O Bus – Can be long and connect many different types of devices – Don’t typically interface directly to memory Use a processor-memory bus or backplane bus Communication bottleneck – Bandwidth limits throughput

Parallel vs. Serial Difficult to run many parallel wires at high speed – Due to clock skew, reflection, coupling Transition from parallel shared busses to serial point-to-point interconnections

Asynchronous I/O Standards Firewire (IEEE 1394) USB (Universal Serial Bus) PCI (Peripheral Component Interconnect) Serial ATA (SATA) Serial Attached SCSI (SAS) – SCSI (Small Computer System Interface)

Synchronous I/O Standards SPI – Serial Peripheral Interface I 2 C or I2C or IIC – Inter-Integrated Circuit

Busses: Asynchronous vs. Synchronous Synchronous – Advantages – Disadvantages Asynchronous – Advantages – Disadvantages

I/O Transactions Need to send address Need to send/receive data May cause a sequence of bus operations

Role of OS in Handling I/O Multiple programs must share the I/O system – Schedule access to I/O for fairness and high sytem throughput – Protect user’s program access rights Handle interrupts that trap to kernel/system/supervisor mode – Similar to handling exceptions generated by a program Handle low-level control of I/O device – This is usually complex – Provides abstractions by supplying routines that handle low-level device operations

Communication required from OS for I/O Devices OS must give commands to I/O devices I/O device must notify OS – Tell it if it completes an operation – Tell it if it encounters an error Transfer data between memory and I/O device

OS Giving Commands to I/O Devices OS must be able to address the device – Special I/O instruction – Memory-mapped I/O OS must read/write I/O device registers

I/O Device notifying the OS I/O device must communicate with the processor Polling Interrupt-driven I/O

Interrupts Asynchronous with respect to instruction execution Need to know what caused the interrupt – Vectored interrupts – Exception/interrupt cause register Interrupt Priority Levels

Transfer Data between I/O Device and Memory Polling versus Interrupts Burden of moving the data and managing the transfer – Processor – Controller DMA (Direct Memory Access) controller

DMA DMA is master and directs reads/writes between itself and memory Steps in a DMA transfer – Processor sets up the DMA – DMA starts operation and arbitrates the interconnect – DMA interrupts the processor once transfer completes Can create cache coherency problems