IMPLEMENTING RISC MULTI CORE PROCESSOR USING HLS LANGUAGE - BLUESPEC LIAM WIGDOR INSTRUCTOR MONY ORBACH SHIREL JOSEF Winter 2013 One Semester Mid-term presentation

PROJECT GOAL Implementing RISC multi core processor using BlueSpec - implement dual core processor with scalability - cores sharing data memory

WHAT HAVE WE DONE SO FAR Learned about BlueSpec principles, syntax and working environment Practiced simple adjustments to the processor code Learned about Single Core, two stage pipeline, processor code

We will use 2 stage pipeline MIPS for each core The Mips BlueSpec code taken from Architecting and Implementing Microprocessors in BlueSpec Shared between cores

Each core 2 stage pipeline separate register file separate instruction memory Control hazard detection ( Epoch )

PROJECT CURRENT STAGE Creating Multi Core processor by combining two single core processors sharing data memory Core 1 Core 2 Data Memory 32 Bit In use (signal)

PROJECT CURRENT STAGE Memory access before the changes Memreq is sent to the data memory in load\store operetion ( During execute stage ) - Memreq contain memory address and data Data is returned from the memory in load operetion

PROJECT CURRENT STAGE Memory access after the changes Adding a signal indicating whether the memory is being accessed If not Then the core can access it Else Wait

NEXT STEPS – PHASE 1 BlueSpec SW simulation - Using BlueSpec compiler to create simulation object files - generate an executable program - providing a convenient way to run the simulation objects

NEXT STEPS - PHASE 2 Comparing results between single core and our Multi Core Using simple bench mark programs : without data memory access with data memory access Comparing : IPC – instruction per cycle Ideally, IPC for Dual Core is 2. Since the processors share data we assume 1< IPC <2

NEXT STEPS - PHASE 3 Testing the design using BlueSpec simulation tools (SCE-MI) For testing : We will use an existing working enviroment ( Project no. D07111 Winter 2012 ) Reading and writing to memories via JTAG The platform enables: Synthesis of design to FPGA via Direct PC Cycle level control using COP ( Co Processor )

PROJECT GANTT Phase 1 2/323/216/29/22/219/112/15/1 29/12 26/1 BlueSpec oriented multi- core design (no cache) CDR prep Exams 9/3 Phase 2

PROJECT GANTT /26/430/323/3 16/3 13/4 conclusions Phase 3