Specification mining for asynchronous controllers Javier de San Pedro† Thomas Bourgeat ‡ Jordi Cortadella† † Universitat Politecnica de Catalunya ‡ Massachusetts Institute of Technology 1

Specification mining FIFO ctrl FIFO ctrl lr rr lara lr+ la+ lr- la- rr+ ra+ rr- ra- C C lr rr ra la Synthesis Specification mining Specification mining 2 Resynthesis

Outline Overview of specification mining Modeling behavioral properties Mining algorithm Results and conclusions 3

a b x y Background a+ b+ y+ b− x+ y+ x− a− y- a+ x+ y+ y- a− x− b+ b- Signal Transition Graph State Graph Netlist Synthesis Specification Mining 4 (Labeled Transition System - LTS) (Petri Net)

Specifications with properties Mined specifications must satisfy a set of behavioral properties – E.g., only show hazard-free behavior Nothing is known about the environment – Initially assume free (unrestricted) env. – Circuit may exhibit hazards under free env. To ensure the specification satisfies the set of properties… – Circuit behavior cannot be changed  Discover constrained environment where the circuit satisfies all properties 5 Environment Input netlist a b x y Free environment × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × ××× × × Hazard

LTS under free environment Free environment a b x y a+ a− a+ a− x− x+ 6 a x × x+ is not persistent under free environment Free environment × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × ××× × × × x+? Select a subset of input transition arcs that satisfy all behavioral properties Constrained env.

Hazards under free environment 7 Free environment a b x y b+ b− a+ a− b+ b− a+ a− b+ b− a+ a− b+ b− a+ a− b+ b− a+ a− b+ b− a+ a− b+ b− a+a− b+ b− a+ a− y− y+ y− x− x+ x− x+ x− y+ x− x+ Free environment × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × ××× × × × × x+ × × × × × × × × × × ×

Constraining the environment 8 Constrained env. a b x y b− a+ b+ a− y− y+ x+ y+ x− Free environment × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × ××× × × Constrained env. Select a subset of input transition arcs that satisfy all behavioral properties

More than one specification 9 Constrained env. #2 a b x y b− a+ b+ a− y− y+ x− Free environment × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × ××× × × x+ Constrained env. #2 There might more than one environment that satisfies the properties

Overview of mining flow 10 Circuit LTS (free env.) LTS (free env.) LTS snippet 1 (constrained env.) LTS snippet 1 (constrained env.) STG 1 LTS snippet 2 (constrained env.) LTS snippet 2 (constrained env.) STG 2 Properties SI DI interfacing … Free environment × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × Constrained env. #2 Constrained env. #1

Outline Overview of specification mining Modeling behavioral properties Mining algorithm Results and conclusions 11

Properties Behavioral properties – Speed-independence – Delay-insensitive interfacing – Multiple independent environments – … Properties of the specification model – Marked Graph – Free Choice – …  All properties modeled using SAT 12

Modeling properties using SAT 13 a+ a− a+ x− x+ a−

Causality patterns in LTS 14 x y y y is persistent x y y x triggers y x y y x disables y Conflict/choiceConcurrencyOrder

Behavioral properties Speed-independence (SI) – Insensitive to gate delays – Property: Only inputs can disable inputs Delay insensitive interfacing (DII) – Insensitive to arrival order of input transitions – Property: Inputs cannot trigger other inputs 15 xy x triggers yx disables y Input Violates DII Output Violates SI InputOutputViolates SI OutputInputViolates SI H. Saito, A. Kondratyev, J. Cortadella, L. Lavagno and A. Yakovlev, What is the cost of delay insensitivity? ICCAD 1999

Example: speed-independence For every state, for every pair (x, y) where x input, y output: 16 x y y x disables y x y y y is persistent xy x triggers yx disables y Input Violates DII Output Violates SI InputOutputViolates SI OutputInputViolates SI

Multi-environments 17 Circuit Environment 1 Environment 2 Environment 3 xy x triggers yx disables y Input Violates DII Only if same env. Output Violates SI InputOutputViolates SI OutputInput Only if same env. Violates SI × × FIFO ctrl FIFO ctrl lr rr lara Left environment Right environment ×

Properties of the specification model Enforce specific structural types of STGs – Enhances visualization, computational cost, … Marked graph – Property: No two signals are in conflict Free choice – Property: Signals in conflict must have the same excitation set (see article) 18 E. Best and R. Devillers, Characterization of the state spaces of live and bounded marked graph Petri nets, Language and Automata Theory 2014.

Outline Overview of specification mining Modeling behavioral properties Mining algorithm Results and conclusions 19

SAT model 20 a+ a− a+ x− x+ a−

Mining algorithm: MaxSAT 21 Free environment Constrained env. #2 Constrained env. #1 No single specification may cover all behavior without violating some property E.g., marked graphs  Discover a set of maximal specifications Except those already in previous snippets!

Overview of mining flow 22 Circuit LTS (free env.) LTS (free env.) LTS snippet 1 (constrained env.) LTS snippet 1 (constrained env.) STG 1 LTS snippet 2 (constrained env.) LTS snippet 2 (constrained env.) STG 2 Properties SI DI interfacing … Petrify

Outline Overview of specification mining Modeling behavioral properties Mining algorithm Results and conclusions 23

Case study: 4-phase latch controller 137 possible speed-independent specifications Synthesized with Petrify, then STGs mined assuming: – Speed-independence – Delay insensitive interfacing – Multi-environment (L, R) All mined STGs identical to original ones 24 G. Birtwistle and K. Stevens Modelling mixed 4-phase pipelines: structures and patterns, ASYNC FIFO ctrl FIFO ctrl lr rr lara

Some 4-phase examples 25

Why multi-environment constraint? 26 FIFO ctrl FIFO ctrl lr rr lara Without multi-environments, 2 snippets are obtained Right env. is triggering left env.

Controllers with choice BenchmarkNum. of snippets Gurobi runtime [seconds] Num. of signals in orig. circuit SM-latch RLM bit variable i/o + 2 internal alloc-outbound i/o + 2 internal vmebus i/o + 1 internal A/D converter ctrl tsend-csm-> 1 hour9 i/o + 2 internal 27 For each benchmark one snippet was identical to the original specification

Example: alloc-outbound 28

Resynthesis: 1-bit variable 29 K. v. Berkel. Handshake Circuits: an Asynchronous Architecture for VLSI Programming Cambridge University Press, Spec. mining Resynthesis (Petrify)

Conclusions Specifications can be successfully recovered for several types of controllers Useful for reverse engineering, resynthesis, compositional verification, … Future work: – Heuristics to handle large exploration spaces – Circuits with bounded delays 30

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BACKUP 32

OLD 33

34 Big LTS template x+ b+ b− a+ a− b+ b− a+ a− b+ b− a+ a− b+ b− a+ a− b+ b− a+ a− b+ b− a+ a− b+ b− a+a− b+ b− a+ a− y− y+ y− x− x+ x− x+ x− y+ x− x+

Snippet 2 35 a+ b+ y+ b− x+ y+ x− a− y- b+ y+ b− y- a+ x+ a− x− a+ x+ y+ a− x− b+ b- b+ y+ b- y- a+ x+ a- x-

LTS under free environment a b x y b+ b− a+ a− b+ b− a+ a− b+ b− a+ a− b+ b− a+ a− b+ b− a+ a− b+ b− a+ a− b+ b− a+ a− b+ b− a+ a− y− y+ 36 y− x− x+ x− x+ x− y+ x− x+ Nothing is known from the environment  Assume free environment All input transitions enabled Reset state Environment Original specification

Constraining environment a b x y b+ b− a+ a− b+ b− a+ a− b+ b− a+ a− b+ b− a+ a− b+ b− a+ a− b+ b− a+ a− b+ b− a+ a− b+ b− a+ a− y− y+ 37 y− x− x+ x− x+ x− y+ x− x+  Speed-independent  Delay-insensitive interfacing Environment Original specification ✓ ✓

Objectives of this work Can we discover a specification of the interface that guarantees a speed-independent behavior of the circuit? 38 a+ b+ y+ b− x+ y+ x− a− Removing input transitions only