Specifications Asic description Constraints Interface with PDM board Planning Summary

3 ASICs Connector Rigid from EC-ANODE Connector toward the PDM board As close as possible Flex from EC-ANODE Specifications: An ASIC is assigned to each MAPMT  36 ASICs have to be distributed on the boards of the EC-back electronic. They should also include the connectors toward the EC-anode and PDM boards as well as all the passive components needed. The idea is to go for 6 boards perpendicular to the PDM mechanical structure. They would be fixed on a mechanical structure perpendicular to the one of the PDM Each board would have 6 connectors (toward EC-anode boards) and 6 ASICs, many passive components and 1 connector toward PDM board. Volume for Electronics: EC_asic, HV box, PDM board PDM Frame With EC_front MAPMT

ASIC BASIC FASIC D 4 3 ASICs, with their associated passive components, on each side of the pcb 6 connectors (68 pins: 64 anodes + 4 gnd) on one top side 1 connector (120 pins) on top side 68 pins68 pins ASIC A 68 pins68 pins ASIC C ASIC E 120 pins ABCDEF 68 pins68 pins 68 pins68 pins 68 pins68 pins 68 pins68 pins

5 Specifications:  Readout MAPMT signals  Consumption: 1mW/channel  Photon counting: 100% trigger (1/3pe, 10 6 Gain)  Charge/time converter input range : 2pc – 200pc (10pe pe)  Radiation hardness Spatial Photomultiplier Array Counting and Integrating ReadOut Chip 1st version received in October 2010 Technology: AMS 0.35µm SiGe Dimensions : 4.6mm x 4.1mm (19 mm²) Power supply: 0-3V Packaging : P(C)QFP240(160)

6 64 channels Preamplifier with individual 8-bit gain adjustment Photo-electron counting (10-bit DACs) – 3 discriminator outputs : Trig_PA, Trig_FSU & Trig_VFS – Multiplexed discriminator outputs to Digital part – Many parameters available Charge to time converters (called KIs) – Designed in collaboration with JAXA/RIKEN – 9 outputs : 8 channels (8-pixel-Sum) + Last Dynode – Many parameters available Continuous Data acquisition & Readout every 2.5  s (GTU) – 8 identical digital module for PC – 1 digital module for KI First version of SPACIROC showed good behavior (intensive lab tests with and without MAPMT)

7 Package: CQFP 160pins by MATRA Quantity: 100 Cost: 105€/asic Delay: – Package material : 2 weeks – 3 prototypes: 2 weeks – 100 asic: 2 weeks One test board has been produced to sort asic – Cabling ok – Firmware is the same as the previous spaciroc test board – Software should be modified to perform automatic tests

2 types of pcbs are foreseen: 8 1 with a straight flexible part Connector on top 1 with a curved flexible part Connector on bottom

9 Connectors choice: EC_asic: HIROSE FX2CA-68S-1.27DSA - Receptacle - Straight type - Dimension=49mm x 7.5mm - Through hole type Not exactly the same pinout => For EC_asic design, we need to know which connector corresponds to which type of EC_anode

10 3 EC_unit + 2 EC_ASIC boards – Curve EC_anode: connector A, C, E – Straigth EC_anode: connector B, D, F One EC_asic reads half of the EC_unit Pmt 1 Pmt 3 Pmt 2 Pmt 4 B CD A EF FE A DC B

Ki input: sum of 8 consecutive anodes Pmt 1Pmt 2 B CD A EF FE A DC B To check the routing feasibility: Schematic simpler: 2 connectors: curve kapton connector A and straight kapton connector B 2 SPACIROC Connector 120pins ki1ki2 ki3ki4 ki3 ki2ki1 ki2ki6 ki1ki5 ki1 ki6ki2

12 The ASIC: SPACIROC (2/3)

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Modifications: – Vertical red parts should be modified Increase area for EC_ASIC boards – Support structures have to be aligned with the holes like the central one otherwise cables do not pass – Need room for the HV boards 14 Material: Aluminum Weight: kg Overall dimensions: 167mm x 128mm x 130mm Available area for elect. : 115mm x 100mm ~ 55 mm As short as possible Pair of EC- ASIC boards Need to study how to screw the boards: EC_asic, HV box and PDM board

Dimension could be 140mm x 110mm

Connector 120 pins should be enough Choice: HIROSE FX2-120P-1.27DS – Header – Right angle type – Dimension=82mm x 7.5mm 16 Input name and number of pinsOutput name and number of pins avdd4Sr_ck1Clk_40n1Adata_ki1Atransmit_on1Adata_pc[7..0]8AOR_ki_sum1Aerror_sc1 vdd_ki2Sr_in1Clk_40p1Bdata_ki1Btransmit_on1Bdata_pc[7..0]8BOR_ki_sum1Berror_sc1 dvvd4sr_out1Clk_gtu_n1Cdata_ki1Ctransmit_on1Cdata_pc[7..0]8COR_ki_sum1Cerror_sc1 VH4Sr_rstb1Clk_gtu_p1Ddata_ki1Dtransmit_on1Ddata_pc[7..0]8DOR_ki_sum1Derror_sc1 gnd14resetb1Val_evt_n1Edata_ki1Etransmit_on1Edata_pc[7..0]8EOR_ki_sum1Eerror_sc1 Select_sc_probe1Val_evt_p1Fdata_ki1Ftransmit_on1Fdata_pc[7..0]8FOR_ki_sum1Ferror_sc1 Loadb_sc1AOR_FSU1COR_FSU1EOR_FSU1 Select_din1BOR_FSU1DOR_FSU1FOR_FSU1 What will be the connection between the EC_ASIC and the PDM board? Kapton or cable ? Who is in charge of this connection

Week 9: 24 Jan-3 Feb – Feasibility routing inputs with 2 through hole connectors Week 10: 5 -9 Mar – Feasibility routing inputs with 2 surface mounted connectors – Schematic of whole EC_asic Week 11-14: 12 Mar- 6Apr – Routing whole EC_asic => the dimensions will be set – Schematic of a test board (test_ec_asic) to check functionalities of one EC_ASIC Week 15-16: Easter holidays Week 17-21: 23 Apr- 25May – Routing test_ec_asic board 17 Production PCBs will be done when the money is available Cabling and component procurement will be managed by us

LAL team manage schematic, routing and production of EC_ASIC To Be Defined: – Who can do the mechanical modifications? – Who is in charge of the connection between EC_ASIC and the PDM board (lack of manpower and time at LAL)? 18