Kanupriya Gulati * Mathew Lovell ** Sunil P. Khatri * * Computer Engineering, Texas A&M University ** Hewlett Packard Company, Fort Collins, CO Efficient Don’t Care Computation for Hierarchical Designs

2 Overview Introduction Introduction Previous Work Previous Work Our Approach Our Approach Approximate Version Approximate Version Example Example Experimental Results Experimental Results Conclusions Conclusions

3 Introduction Synthesis tools typically flatten a hierarchical design. Advantage: provides good flexibility for optimizations. Disadvantage: Potentially huge representation after circuit flattening. We describe a BDD-based method for computing Don’t Cares while retaining Hierarchy. Advantage: we can compute Don’t Cares for circuits in which the flattened approach fails. Advantage: literal count reduction is superior compared with other approaches Disadvantage: cannot invoke the complete flexibility in theory Disadvantage: good partitioning of the circuit important.

4 Additional Advantages Enables existing tools to handle significantly larger designs. Designers can concentrate on critical modules and optimize them more aggressively Alternately, a designer can optimize different modules with different objectives. Instances of the same module can be optimized separately. If all modules need to be identical after optimization, we can intersect the don’t cares of all identical modules and then optimize them

5 Previous Work Very little, to the best of our knowledge Very little, to the best of our knowledge Hierarchical optimization approach proposed by Hachtel and Lightner [1] about 19 years ago, but its implementation and effectiveness were not validated Hierarchical optimization approach proposed by Hachtel and Lightner [1] about 19 years ago, but its implementation and effectiveness were not validated In [2], sub-circuits were treated as black-boxes for optimization purposes, and all information across hierarchy boundaries was lost In [2], sub-circuits were treated as black-boxes for optimization purposes, and all information across hierarchy boundaries was lost In [3], hierarchy was exploited in don’t care computation of MUX-based networks. Don’t cares were extracted from the datapath, and used to optimize the control logic. In [3], hierarchy was exploited in don’t care computation of MUX-based networks. Don’t cares were extracted from the datapath, and used to optimize the control logic. Circuit model therefore quite restrictive. Circuit model therefore quite restrictive. [1] G. Hachtel and M. Lightner, “Don't care conditions in top down synthesis,” ICCAD 87. [2] T.-H. Liu, K. Sajid, A. Aziz, et al., “Optimizing designs containing black boxes," DAC 97. [3] S. Bhattacharya, F. Brglez, and S. Dey, “Transformation and resynthesis for testability for RTL-level control-data path Specifications”, IEEE TVLSI, Sept. 1993

6 Our Approach - Overview Hierarchical blocks (sub-circuits) of the design initially sorted in topological order from top-level primary inputs to top-level primary outputs Hierarchical blocks (sub-circuits) of the design initially sorted in topological order from top-level primary inputs to top-level primary outputs Compute don’t cares at input and output interfaces of hierarchical blocks Compute don’t cares at input and output interfaces of hierarchical blocks Don’t cares computed by performing image computation Don’t cares computed by performing image computation Perform approximate image computation if full image cannot be computed Perform approximate image computation if full image cannot be computed Don’t cares of a sub-circuit n are used by other sub-circuits whose inputs are driven by n. Don’t cares of a sub-circuit n are used by other sub-circuits whose inputs are driven by n. Sequential designs handled easily (make latch PIs = sub-circuit POs, latch POs = sub-circuit PIs). Sequential designs handled easily (make latch PIs = sub-circuit POs, latch POs = sub-circuit PIs). Finally, optimize each hierarchical block using the don’t cares computed for it. Finally, optimize each hierarchical block using the don’t cares computed for it.

7 x1x1 x2x2 x3x3 y1y1 y2y2 01 Computation of Interface Don’t cares Our Approach

8 x1x1 x2x2 x3x3 y1y1 y2y2 01

9 x1x1 x2x2 x3x3 y1y1 y2y2 01 y w

10 Approximate Computation ROBDDs of the characteristic functions T(x,y) and T(y,w) ROBDDs of the characteristic functions T(x,y) and T(y,w) Could be badly behaved, and may result in a memory explosion Could be badly behaved, and may result in a memory explosion Might cause image computation to fail. Might cause image computation to fail. Calculate Approximate Characteristic functions T’(x’,y) and T’(y’,w) such that the size of the ROBDD is bounded by a size S Calculate Approximate Characteristic functions T’(x’,y) and T’(y’,w) such that the size of the ROBDD is bounded by a size S This computation is conservative. (proof in paper) This computation is conservative. (proof in paper)

11 Approximate Computation In general, there are common variables between x and x’, as well as between y and y’. In general, there are common variables between x and x’, as well as between y and y’. Hence the care sets found during the input interface care set computation can be used for output interface care set computation. Hence the care sets found during the input interface care set computation can be used for output interface care set computation.

12 Example Topologically sort blocks DC for Q2’s input is NULL DC for Q2’s output is { 10 } DC for Q1’s input is {00-, 11-} DC for top level circuit is {0001, 100-, -10-, -11-} on variables Q1 y, Q1 x, Q2 y and Q2 x

13 Algorithm Compute_Don’t_Cares(hrcNode, careSet) { Create network for hrcNode i.e. for the current level; Topologically order children; for each child in topological order do inputImage ← Compute child’s input care set; outputPreImage ← outputPreImage ^ Compute_Don’t_Care(child, inputImage); end for outputImage ← Compute this level’s output care set; write out blif file for optimization in SIS return outputImage; }

14 Implementation Don’t Care computation implemented in VIS Don’t Care computation implemented in VIS Takes into account several details Takes into account several details Computing the conjunction of don’t care sets of different sub-circuits at the same level of hierarchy Computing the conjunction of don’t care sets of different sub-circuits at the same level of hierarchy Conduct variable substitution to change the support variables for the don’t cares from formal variables to actual variables (and vice versa) Conduct variable substitution to change the support variables for the don’t cares from formal variables to actual variables (and vice versa) Extensions to sequential designs Extensions to sequential designs Create hierarchical data structures in VIS to Create hierarchical data structures in VIS to Compute input and output interface don’t cares, while retaining hierarchy Compute input and output interface don’t cares, while retaining hierarchy What we currently do not account for What we currently do not account for True sequential don’t cares, or CODCs of sub-circuits True sequential don’t cares, or CODCs of sub-circuits Also, cyclic dependencies between sub-circuits not handled (can handle it using a fixpoint computation) Also, cyclic dependencies between sub-circuits not handled (can handle it using a fixpoint computation) Sub-circuit optimization done in SIS Sub-circuit optimization done in SIS

15 Experimental Setup Used benchmark designs from VIS-2.0 Used benchmark designs from VIS-2.0 Designs that had hierarchy Designs that had hierarchy No non-deterministic variables. No non-deterministic variables. Also used randomly generated benchmarks using the MCNC benchmark suite (denoted “rex” in the results) Also used randomly generated benchmarks using the MCNC benchmark suite (denoted “rex” in the results) Threshold S set as 50,000 BDD nodes. Threshold S set as 50,000 BDD nodes. Experiments conducted on 2.4GHz Celeron CPU with 512 MB RAM, running Linux. Experiments conducted on 2.4GHz Celeron CPU with 512 MB RAM, running Linux. Our approach was compared with Our approach was compared with Flat optimization of the hierarchical design in SIS Flat optimization of the hierarchical design in SIS Optimization of the individual sub-circuits in the hierarchy without any interface don’t cares, using SIS Optimization of the individual sub-circuits in the hierarchy without any interface don’t cares, using SIS

16 Results

17 Conclusions We compute don’t cares at the input and output interfaces of a hierarchical design using an image computation process. We compute don’t cares at the input and output interfaces of a hierarchical design using an image computation process. In case exact image cannot be computed, compute the largest approximate image. In case exact image cannot be computed, compute the largest approximate image. Hierarchical instances are optimized separately using traditional techniques (full_simplify in SIS). Hierarchical instances are optimized separately using traditional techniques (full_simplify in SIS). Circuit never flattened Circuit never flattened Allows don’t care computation for significantly larger designs than a traditional flat approach Allows don’t care computation for significantly larger designs than a traditional flat approach Experimental results demonstrate an 8-10% reduction in literal count for large hierarchical designs, with good run times. Experimental results demonstrate an 8-10% reduction in literal count for large hierarchical designs, with good run times. In many cases, flattened optimization is infeasible, while our approach completes successfully. In many cases, flattened optimization is infeasible, while our approach completes successfully.

18 Thank You !!