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JET Algorithm Attila Hidvégi. Overview FIO scan in crate environment JET Algorithm –Hardware tests (on JEM 0.2) –Results and problems –Some VHDL tips.

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Presentation on theme: "JET Algorithm Attila Hidvégi. Overview FIO scan in crate environment JET Algorithm –Hardware tests (on JEM 0.2) –Results and problems –Some VHDL tips."— Presentation transcript:

1 JET Algorithm Attila Hidvégi

2 Overview FIO scan in crate environment JET Algorithm –Hardware tests (on JEM 0.2) –Results and problems –Some VHDL tips –Ongoing work on jet code Other work in Stockholm

3 FIO scan in crate environment (one of two JEMs)

4 Delay scan for individual FPGAs

5 Delay scan for two JEMs (same deskew clock settings)

6 It is important to equalize timing between JEMs

7 Hardware tests of Jet algorithm Originally only jet multiplicities recorded; insufficient for diagnostics. New firmware was needed. All inputs and outputs needed to be recorded. Same spy memory and software as for FIO scan. JET Spy memory Data in Configurations

8 JET Algorithm – Results All input data is received properly (↕). Synthesis tool reports maximum delay of 11.2 ns and 26.4 ns, for 80 and 40 MHz clocks, respectively. This is the maximum achievable result for current VHDL code. Results from hardware tests show random errors!

9 Most likely cause of the problem Only adders still use 5-bit serial arithmetics –Virtex architecture more suited to parallel arithmetic with fast- carry chains. Adders are the slowest component of the algorithm. The errors are intermittent, suggesting timing problems –Sums occasionally wrong. –Sometimes cause incorrect threshold passes –More often give wrong ROI positions for random data The timing problem of the adders can not be resolved without a major rewriting. JET algorithm is being rewritten from scratch.

10 New design for the Jet code It will be flexible. Generic variables will decide the configuration. The code has to be short, so that one can modify it easily. Try to minimize size and latency. Use only parallel arithmetics, and take full advantage of the fast carry architecture available in Virtex FPGAs. Let the synthesis tool do the hard work. It needs to work…

11 Making it flexible means:

12 Minimizing the latency and size Making all the summation and the local maximum finding in the first clock cycle, allows us to remove all the pipelines. To achieve all the sumation in the first clock cycle tha adders have to be fast. It is important to decide the multiplexing as early as possible. The multiplexing needs to be carried out on the right place. It is important to remember that the size of a multiplexer (2:1), an adder or a comparator is equal, since they use the same logic rescources.


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