1. Input/Output

2. Input/Output Problems zWide variety of peripherals yDelivering different amounts of data yAt different speeds yIn different formats zAll slower than CPU and RAM zNeed I/O modules

3. Input/Output Module zInterface to CPU and Memory zInterface to one or more peripherals

4. External Devices zHuman readable yScreen, printer, keyboard zMachine readable yMonitoring and control zCommunication yModem yNetwork Interface Card (NIC)

5. I/O Module Function zControl & Timing zCPU Communication zDevice Communication zData Buffering zError Detection

6. I/O Steps zCPU checks I/O module device status zI/O module returns status zIf ready, CPU requests data transfer zI/O module gets data from device zI/O module transfers data to CPU zVariations for output, DMA, etc.

7. I/O Module Diagram Data Register Status/Control Register External Device Interface Logic External Device Interface Logic Input Output Logic Data Lines Address Lines Data Lines Data Status Control Data Status Control Systems Bus Interface External Device Interface

8. Input Output Techniques zProgrammed zInterrupt driven zDirect Memory Access (DMA)

9. Programmed I/O zCPU has direct control over I/O ySensing status yRead/write commands yTransferring data zCPU waits for I/O module to complete operation

10. Programmed I/O - detail zCPU requests I/O operation zI/O module performs operation zI/O module sets status bits zCPU checks status bits periodically zI/O module does not inform CPU directly zI/O module does not interrupt CPU zCPU may wait or come back later

11. Direct Memory Access zInterrupt driven and programmed I/O require active CPU intervention yTransfer rate is limited yCPU is tied up zDMA is the answer

12. DMA Function zAdditional Module (hardware) on bus zDMA controller takes over from CPU for I/O

13. DMA Operation zCPU tells DMA controller:- yRead/Write yDevice address yStarting address of memory block for data yAmount of data to be transferred zCPU carries on with other work zDMA controller deals with transfer zDMA controller sends interrupt when finished

14. DMA Transfer Cycle Stealing zDMA controller takes over bus for a cycle zTransfer of one word of data zNot an interrupt yCPU does not switch context zCPU suspended just before it accesses bus yi.e. before an operand or data fetch or a data write

15. DMA Configurations (1) zSingle Bus, Detached DMA controller zEach transfer uses bus twice yI/O to DMA then DMA to memory zCPU is suspended twice CPU DMA Controller I/O Device I/O Device Main Memory

16. DMA Configurations (2) zSingle Bus, Integrated DMA controller zController may support >1 device zEach transfer uses bus once yDMA to memory zCPU is suspended once CPU DMA Controller I/O Device I/O Device Main Memory DMA Controller I/O Device

17. DMA Configurations (3) zSeparate I/O Bus zBus supports all DMA enabled devices zEach transfer uses bus once yDMA to memory zCPU is suspended once CPU DMA Controller I/O Device I/O Device Main Memory I/O Device I/O Device