1. High speed signal transmission Jan Buytaert

2. Topics Electrical standards: CML,LVDS, SLVS Equalization. Testbench of a readout slice. Vacuum feed-throughs. Cable choice (development)

3. ‘Current scenario’ There is consensus in the VELO group to have the electro/optical transition outside the vacuum vessel. The ‘Building block’ for modules will be 6 VELOpix asics. Each asics will have ~4 high speed outputs (at ~ 4 Gbit/s). Total number of datalinks per ‘building block’ = 24. Total number of datalinks in system = (23 x 4) x 24 = 2208.

4. CML (current mode logic) + popular in electric high speed signaling on pcb. (laser drivers, serdes) + simple output stage. +compatible with low CMOS supply voltages (e.g. 1.2V) + voltage swing can be controlled by current source (thus power consumption !). - asymmetric drive strength for rising/falling edges. - not fully differential transmission (the mirror current is carried by the shield, not by the second conductor...) This is OK for pcb short traces, but less adapted to differential cable transmission. + Can be double-terminated when ac-coupled. i or 0 0 or i i

5. LVDS. + popular in electric high speed signaling on cable. - More complex output stage. : 3mA current steering - not compatible with low CMOS supply voltages (e.g. 1.2V) - Voltage swing 2x300mV on 100 ohm, common mode =1.2V + symmetric drive strength for rising/falling edges. + fully differential transmission (the mirror current is carried by the second conductor, the shield does not carry transient currents.) + This is OK for pcb and differential cable transmission. +‘Floating’ termination. + proven to be an excellent digital I/O standard on sensitive analog asics ! + i or -i i i Zdiff

6. sLVS (scalable low voltage signalling) + popular in electric high speed signaling for imaging and portables. + used for e-links in GBT project (320Mbit/s). + compatible with low CMOS supply voltages ( common mode = 200mV) + voltage swing could be controlled by current source 0.5mA to 2mA (thus power consumption !). - differential voltage swing on 100 ohm : 100mV to 400mV. + symmetric drive strength for rising/falling edges. + fully differential transmission (the return current is carried by the second conductor, the shield does not carry transient currents.) This is OK for pcb and differential cable transmission.

7. Equalisation. Will most likely be required to transmit 5Gbit/s over 2m low mass cables (high distortion) and connectors. Commercial driver : ONET1101L from TI ? – 11.3 Gbps VCSEL Laser Diode Driver. – Programmable modulation and bias current. – Programmable input equalizer. – used in ‘versatile link project’ as commercial laser driver. – Radiation dose and SEU tolerant ??? We could try to qualify ? Include in VELOpix ? – See presentation by BRUCO (+NIKHEF) on high speed link. Equalization by PWM technique.

8. Testbench of a readout slide. Propose to start from the BERT (bit error rate tester) developed at CERN by ‘versatile link project’. FPGA based. Experiment with low mass cables and connectors, laser drivers,etc … Should follow closely the ‘ATLAS-CMS optical transmission working group’ (e.g. Atlas liquid argon upgrade very similar to VELO !) Since we have 24 links per VELOpix module, EMI/EMS (crosstalk) is very important.