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The trigger-less TBit/s readout for the Mu3e experiment Dirk Wiedner On behalf of the Mu3e collaboration 24 Sep 20131Dirk Wiedner TWEPP2013.

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Presentation on theme: "The trigger-less TBit/s readout for the Mu3e experiment Dirk Wiedner On behalf of the Mu3e collaboration 24 Sep 20131Dirk Wiedner TWEPP2013."— Presentation transcript:

1 The trigger-less TBit/s readout for the Mu3e experiment Dirk Wiedner On behalf of the Mu3e collaboration 24 Sep 20131Dirk Wiedner TWEPP2013

2 The Mu3e Signal 9/20/2012Dirk Wiedner, Mu3e collaboration2 μ → eee rare in SM Enhanced in: o Super-symmetry o Grand unified models o Left-right symmetric models o Extended Higgs sector o Large extra dimensions  Rare decay (BR<10 -12, SINDRUM) For BR O(10 -16 )  >10 16 muon decays  High decay rates O(10 9 muon/s)

3 The Mu3e Experiment 9/20/2012Dirk Wiedner, Mu3e collaboration3 Target double hollow cone Silicon pixel tracker Scintillating fiber tracker Recurl station Tile hodoscope Muon beam O(10 9 /s) Helium atmosphere 1 T B-field

4 The Mu3e Experiment 9/20/2012Dirk Wiedner, Mu3e collaboration4 Target double hollow cone Silicon pixel tracker Scintillating fiber tracker Recurl station Tile hodoscope Muon beam O(10 9 /s) Helium atmosphere 1 T B-field

5 The Mu3e Experiment 9/20/2012Dirk Wiedner, Mu3e collaboration5 Target double hollow cone Silicon pixel tracker Scintillating fiber tracker Recurl station Tile hodoscope Muon beam O(10 9 /s) Helium atmosphere 1 T B-field

6 The Mu3e Experiment 9/20/2012Dirk Wiedner, Mu3e collaboration6 Target double hollow cone Silicon pixel tracker Scintillating fiber tracker Recurl station Tile hodoscope Muon beam O(10 9 /s) Helium atmosphere 1 T B-field

7 The Mu3e Experiment 9/20/2012Dirk Wiedner, Mu3e collaboration7 Target double hollow cone Silicon pixel tracker Scintillating fiber tracker Recurl station Tile hodoscope Muon beam O(10 9 /s) Helium atmosphere 1 T B-field

8 Readout Requirements 24 Sep 2013Dirk Wiedner TWEPP20138 2.5 GHz muon decays 50 ns readout frames (pixel) O(5000) pixel chips O(7000) scintillating fibers O(7000) timing tiles Online filtering

9 Timing Detectors 24 Sep 2013Dirk Wiedner TWEPP20139 Scintillating fiber hodoscope Timing tiles On detector zero- suppression Poster Session: o STiC - A Mixed Mode Silicon- Photomultiplier Readout ASIC for Time-of-Flight Applications (Tobias Harion) O(7000) fibers O(7000) tiles

10 Silicon Pixel Detector 24 Sep 2013Dirk Wiedner TWEPP201310 Inner double layer Outer double layer Re-curl layers o Both sides (x2) Sensor size o 1x2 cm 2 inner layers o 2x2 cm 2 outer layers 180 inner sensors 4680 outer sensors

11 HV-MAPS 2/5/2013Dirk Wiedner, Mu3e collaboration11 H igh V oltage M onolithic A ctive P ixel S ensors HV-CMOS technology Reversely biased ~60V o Charge collection via drift  Fast O(100 ns) o Thinning to < 50 μm possible by Ivan Peric I. Peric, A novel monolithic pixelated particle detector implemented in high- voltage CMOS technology Nucl.Instrum.Meth., 2007, A582, 876

12 HV-MAPS 2/5/2013Dirk Wiedner, Mu3e collaboration12 H igh V oltage M onolithic A ctive P ixel S ensors HV-CMOS technology Reversely biased ~60V o Charge collection via drift  Fast O(100 ns) o Thinning to < 50 μm possible by Ivan Peric I. Peric, A novel monolithic pixelated particle detector implemented in high- voltage CMOS technology Nucl.Instrum.Meth., 2007, A582, 876

13 HV-MAPS 2/5/2013Dirk Wiedner, Mu3e collaboration13 H igh V oltage M onolithic A ctive P ixel S ensors HV-CMOS technology Reversely biased ~60V o Charge collection via drift  Fast O(100 ns) o Thinning to < 50 μm possible Integrated readout electronics o Zero suppression o 800Mbit/s serial LVDS outputs by Ivan Peric I. Peric, A novel monolithic pixelated particle detector implemented in high- voltage CMOS technology Nucl.Instrum.Meth., 2007, A582, 876

14 HV-MAPS 2/5/2013Dirk Wiedner, Mu3e collaboration14 H igh V oltage M onolithic A ctive P ixel S ensors HV-CMOS technology Reversely biased ~60V o Charge collection via drift  Fast O(100 ns) o Thinning to < 50 μm possible Integrated readout electronics o Zero suppression o 800Mbit/s serial LVDS outputs by Ivan Peric I. Peric, A novel monolithic pixelated particle detector implemented in high- voltage CMOS technology Nucl.Instrum.Meth., 2007, A582, 876

15 Pixel Readout Scheme 24 Sep 2013Dirk Wiedner TWEPP201315

16 Pixel Readout Scheme 24 Sep 2013Dirk Wiedner TWEPP201316 Pixel logic o Pixel address (8 bit) o Frame number (4 bit) o 50 ns frames Column logic o Pixel data o Column address o Coarse time Frame logic o Super Frame o Contains 16 x 50 ns readout frames o + Sensor header Readout buffer Serializer and fast link(s) Pixel address Pixel Logic Column Logic Frame logic Readout buffer Serializer Fine time Coarse time Coarse time Column address Column address

17 Pixel Readout Scheme 24 Sep 2013Dirk Wiedner TWEPP201317 Pixel logic o Pixel address (8 bit) o Frame number (4 bit) o 50 ns frames Column logic o Pixel data o Column address o Coarse time Frame logic o Super Frame o Contains 16 x 50 ns readout frames o + Sensor header Readout buffer Serializer and fast link(s) Pixel address Pixel Logic Column Logic Frame logic Readout buffer Serializer Frame logic Readout buffer Serializer 8 bit Fine time 4 bit 12 bit Coarse time Coarse time Column address Column address

18 Pixel Readout Scheme 24 Sep 2013Dirk Wiedner TWEPP201318 Pixel logic o Pixel address (8 bit) o Frame number (4 bit) o 50 ns frames Column logic o Pixel data o Column address o Coarse time Frame logic o Super Frame o Contains 16 x 50 ns readout frames o + Sensor header Readout buffer Serializer and fast link(s) Pixel address Pixel Logic Column Logic Frame logic Readout buffer Serializer Frame logic Readout buffer Serializer 8 bit Fine time 4 bit 12 bit Coarse time Column address 12 bit 8 bit 32 bit

19 Pixel Readout Scheme 24 Sep 2013Dirk Wiedner TWEPP201319 Pixel logic o Pixel address (8 bit) o Frame number (4 bit) o 50 ns frames Column logic o Pixel data o Column address o Coarse time Frame logic o Contains 16 x 50 ns readout frames o + Sensor header  Super Frame Readout buffer Serializer and fast link(s) Pixel address Pixel Logic Column Logic Frame logic Readout buffer Serializer 8 bit Fine time 4 bit 12 bit Coarse time Coarse time Column address Column address 32 bit 4 x serial @ 800 Mb/s 12 bit 8 bit

20 Data Link Scheme From detector slices to time slices 24 Sep 2013Dirk Wiedner TWEPP201320

21 Link Overview 24 Sep 2013Dirk Wiedner TWEPP201321 Front end links o Pixel sensor to on-detector FPGA 400 – 800 Mbit/s LVDS o Timing detector readout Optical links from detector o Front end FPGAs o … to readout boards o 5 Gbit/s Optical links in counting room o Off-detector read out boards o …to PC Farm

22 Link Overview 24 Sep 2013Dirk Wiedner TWEPP201322 Front end links o Pixel sensor to on-detector FPGA 400 – 800 Mbit/s LVDS o Timing detector readout Optical links from detector o Front end FPGAs o … to readout boards o 5 Gbit/s Optical links in counting room o Off-detector read out boards o …to PC Farm Pixel Sensor Silicon FPGAs x86 Readout board x12 Readout board x12 PC x48 PC x48

23 Link Overview 24 Sep 2013Dirk Wiedner TWEPP201323 Front end links o Pixel sensor to on-detector FPGA 400 – 800 Mbit/s LVDS o Timing detector readout Optical links from detector o Front end FPGAs o … to readout boards o 5 Gbit/s Optical links in counting room o Off-detector read out boards o …to PC Farm Pixel Sensor FiberTile Pixel Sensor FiberTile Pixel Sensor FiberTile Pixel Sensor FiberTile Silicon FPGAs x86 Fiber FPGAs x48 Tile FPGAs x48 Readout board x16 Readout board x16 Readout board x8 Readout board x8 Readout board x8 Readout board x8 x6336x7000 PC x48 PC x48 O(8Tbit/s)

24 Tile Link Overview 24 Sep 2013Dirk Wiedner TWEPP201324 Front end links o Pixel sensor to on-detector FPGA 400 – 800 Mbit/s LVDS o Timing detector readout Optical links from detector o Front end FPGAs o … to readout boards o 5 Gbit/s Optical links in counting room o Off-detector read out boards o …to PC Farm Pixel Sensor Fiber Pixel Sensor Fiber Tile Pixel Sensor Fiber Tile Pixel Sensor Fiber Tile Silicon FPGAs x86 Fiber FPGAs x48 Fiber FPGAs x48 Tile FPGAs x48 Tile FPGAs x48 Readout board x16 Readout board x16 Readout board x8 Readout board x8 Readout board x8 Readout board x8 PC x48 PC x48 x376

25 Link Overview 24 Sep 2013Dirk Wiedner TWEPP201325 Front end links o Pixel sensor to on-detector FPGA 400 – 800 Mbit/s LVDS o Timing detector readout Optical links from detector o Front end FPGAs o … to readout boards o 5 Gbit/s Optical links in counting room o Off-detector read out boards o …to PC Farm Pixel Sensor Fiber Tile Pixel Sensor Fiber Tile Pixel Sensor Fiber Tile Pixel Sensor Fiber Tile Silicon FPGAs x86 Fiber FPGAs x48 Tile FPGAs x48 Readout board x16 Readout board x16 Readout board x8 Readout board x8 Readout board x8 Readout board x8 PC x48 PC x48 x376x192 O(4Tbit/s)

26 Link Overview 24 Sep 2013Dirk Wiedner TWEPP201326 Front end links o Pixel sensor to on-detector FPGA 400 – 800 Mbit/s LVDS o Timing detector readout Optical links from detector o Front end FPGAs o … to readout boards o 5 Gbit/s Optical links in counting room o Off-detector read out boards o …to PC Farm Pixel Sensor Fiber Tile Pixel Sensor Fiber Tile Pixel Sensor Fiber Tile Pixel Sensor Fiber Tile Silicon FPGAs x86 Silicon FPGAs x86 Fiber FPGAs x48 Fiber FPGAs x48 Tile FPGAs x48 Tile FPGAs x48 Readout board x16 Readout board x16 Readout board x8 Readout board x8 Readout board x8 Readout board x8 PC x48 x192 x96 O(4Tbit/s)

27 Front End FPGAs 24 Sep 2013Dirk Wiedner TWEPP201327 FPGAs on detector o 86 (+96) pieces Receive sensor data o 108 LVDS inputs 5 Gbit/s outputs o 8 optical links o … to counting house Switching data between readout boards farms A-D Front end FPGA 800 Mbit/s LVDS in x 108 5 Gbit/s optical Readout board A Readout board A Pixel Sensor Readout board B Readout board B Readout board C Readout board C Readout board D Readout board D

28 Front End FPGAs 24 Sep 2013Dirk Wiedner TWEPP201328 FPGAs on detector o 86 (+96) pieces Receive sensor data o 108 LVDS inputs 5 Gbit/s outputs o 8 optical links o … to counting house Switching data between readout boards farms A-D Front end FPGA 800 Mbit/s LVDS in x 108 5 Gbit/s optical Readout board A Readout board A Pixel Sensor Readout board B Readout board B Readout board C Readout board C Readout board D Readout board D

29 Front End FPGAs 24 Sep 2013Dirk Wiedner TWEPP201329 FPGAs on detector o 86 (+96) pieces Receive sensor data o 108 LVDS inputs 5 Gbit/s outputs o 8 optical links o … to counting house Switching data between readout boards farms A-D Front end FPGA 800 Mbit/s LVDS in x 108 5 Gbit/s optical Readout board A Readout board A Pixel Sensor Readout board B Readout board B Readout board C Readout board C Readout board D Readout board D

30 Front End FPGAs 24 Sep 2013Dirk Wiedner TWEPP201330 FPGAs on detector o 86 (+96) pieces Receive sensor data o 108 LVDS inputs 5 Gbit/s outputs o 8 optical links o … to counting house Switching data between readout boards farms A-D Front end FPGA 800 Mbit/s LVDS in x 108 5 Gbit/s optical Readout board A Readout board A Pixel Sensor Readout board B Readout board B Readout board C Readout board C Readout board D Readout board D

31 Front end FPGA Readout Board 24 Sep 2013Dirk Wiedner TWEPP201331 FPGA readout boards o 4 per sub-detector 5 Gbit/s optical inputs o 16-28 inputs 10 Gbit/s optical output o 12 outputs to PCs Switching network o A-D sub-farms o One output per PC Readout board 5 Gbit/s Optical x28 PC 10 Gbit/s Optical PC Sub-farm A Front end FPGA Front end FPGA Front end FPGA PC x12

32 Readout Board 24 Sep 2013Dirk Wiedner TWEPP201332 FPGA readout boards o 4 per sub-detector 5 Gbit/s optical inputs o 16-28 inputs 10 Gbit/s optical output o 12 outputs to PCs Switching network o A-D sub-farms o One output per PC Front end FPGA Readout board 5 Gbit/s Optical x28 PC 10 Gbit/s Optical PC Front end FPGA Front end FPGA Front end FPGA PC Sub-farm A x12

33 GPU-PC 24 Sep 2013Dirk Wiedner TWEPP201333 PC with GPU 10 Gbit/s Fiber input o 8 inputs from sub- detectors Data filtering o Timing Filter on FPGA o Track filter on GPU o Data to tape < 100 MB/s FPGA PCIe board GPU computer Optical mezzanine connectors

34 GPU-PC 24 Sep 2013Dirk Wiedner TWEPP201334 PC with GPU 10 Gbit/s Fiber input o 8 inputs from sub- detectors Data filtering o Timing Filter on FPGA o Track filter on GPU o Data to tape < 100 MB/s GPU computer

35 Readout board GPU-PC 24 Sep 2013Dirk Wiedner TWEPP201335 PC with GPU 10 Gbit/s Fiber input o 8 inputs from sub- detectors Data filtering o Timing Filter on FPGA o Track filter on GPU o Data to tape < 100 MB/s PC 10 Gbit/s Optical x8 PC 10 Gbit/s Optical x8 A Readout board B x8 Readout board

36 Timing Filter 24 Sep 2013Dirk Wiedner TWEPP201336 Entire event on PCIe FPGA Tile and Fiber data o Easy to match o Look for three tracks Reject data without three hits o … inside time interval 1 3 2

37 Timing Filter 24 Sep 2013Dirk Wiedner TWEPP201337 Entire event on PCIe FPGA Tile and Fiber data o Easy to match o Look for three tracks Reject data without three hits o … inside time interval 1 3 2

38 Vertex Filter 24 Sep 2013Dirk Wiedner TWEPP201338 Entire event on GPU Large target o Large spread of muons o Easy vertex separation Reject data without three tracks o … inside area interval on target 1 3 2

39 Vertex Filter 24 Sep 2013Dirk Wiedner TWEPP201339 Entire event on GPU Large target o Large spread of muons o Easy vertex separation Reject data without three tracks o … inside area interval on target 1 3 2

40 Summary Mu3e has 280M pixels @ >10 9 muons/s >1 Tbit/s data 0-suppressed serial data from active pixel sensors Switched optical network GPU filter farm with optical inputs 24 Sep 2013Dirk Wiedner TWEPP201340 ++

41 Backup Slides 24 Sep 2013Dirk Wiedner TWEPP201341

42 Physics Motivation 9/20/2012Dirk Wiedner, Mu3e collaboration42 Standard model: No lepton flavor violation Lepton flavor violation?

43 Physics Motivation 9/20/2012Dirk Wiedner, Mu3e collaboration43 Standard model: No lepton flavor violation, but: o Neutrino mixing o Branching ratio <10 -50 →unobservable Lepton flavor violation: μ + →e + e - e +

44 The Mu3e Signal 9/20/2012Dirk Wiedner, Mu3e collaboration44 μ → eee rare in SM Enhanced in: o Super-symmetry o Grand unified models o Left-right symmetric models o Extended Higgs sector o Large extra dimensions

45 The Mu3e Background 9/20/2012Dirk Wiedner, Mu3e collaboration45 Combinatorial background o μ + →e + νν & μ + →e + νν & e + e - o many possible combinations  Good time and  Good vertex resolution required

46 The Mu3e Background 9/20/2012Dirk Wiedner, Mu3e collaboration46 μ + →e + e - e + νν o Missing energy (ν)  Good momentum resolution (R. M. Djilkibaev, R. V. Konoplich, Phys.Rev. D79 (2009) 073004)

47 Pixel Sensor Links 24 Sep 2013Dirk Wiedner TWEPP201347 Vertex Sensor chips o 180 chips o 4 LVDS links o 800 Mbit/s per link Central Silicon Tracker o 936 chips o 2 LVDS links o 800 Mbit/s Recurl stations o 3744 chips o 1 LVDS link o 400 Mbit/s

48 Pixel Sensor Links 24 Sep 2013Dirk Wiedner TWEPP201348 Vertex Sensor chips o 180 chips o 4 LVDS links o 800 Mbit/s per link Central Silicon Tracker o 936 chips o 2 LVDS links o 800 Mbit/s Recurl stations o 3744 chips o 1 LVDS link o 400 Mbit/s Pixel Sensor 800 Mbits/s Front end FPGA

49 Front End FPGAs 24 Sep 2013Dirk Wiedner TWEPP201349 FPGAs on detector o 86 (+96) pieces Receive sensor data o 108 LVDS inputs 5 Gbit/s outputs o 8 optical links o … to counting house Switching between readout boards A-D Optical transceiver FE board

50 Average Occupancies 24 Sep 2013Dirk Wiedner TWEPP201350 All numbers per frame of 50 ns Vertex detector o 2 hits per sensor Central silicon tracker o 0.6 hits per sensor Recurl stations o 0.13 hit per sensor Fiber hodoscope o 0.16 hits per fiber Timing tiles o 0.09 hits per tile Tile occupancies

51 Maximum Occupancies 24 Sep 2013Dirk Wiedner TWEPP201351 All numbers per frame of 50 ns Vertex detector o 5 hits per sensor Central silicon tracker o 2 hits per sensor Recurl stations o 1 hit per sensor Fiber hodoscope o 0.24 hits per fiber Timing tiles o 0.14 hits per tile φ z Vertex occupancies

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