1. Organization for Micro-Electronics desiGn and Applications Ludovic Raux OMEGA microelectronics group Ecole Polytechnique & CNRS IN2P3 http://omega.in2p3.fr SPIROC status : production run and modifications implemented for SPIROC2d

2. OMEGA Engineering run 2014 Engineering run in AMS 0.35 µm SiGe in January 2015 –Several chips will be produced. We will take the opportunity to submit a new SPIROC2d –3 CALICE chips submitted: SPIROC2d, HARDROC3a, MICROROC1a –2 analogue variants of SPIROC: CITIROC and EASIROC –Dedicated chip for fast timing and high timing resolution SiPM applications: PETIROC and TRIROC –Chips for Photomultiplier : MAROC and PARIROC SPIROC 2d Analog HCAL (SiPM) 36 ch. 32mm² Mardi 16 décembre 2014 - AHCAL main meeting - DESY - Ludovic RAUX 2

3. SPIROC 2d SPIROC 2d will be an intermediate step before switching to 3rd generation chips 3rd generation ROC chips: –The 64 (HR and SK) or 36 (SP) channels will be independent for zero supress, meaning that only the hit channels will be memorized in the SCA –I2C link for the slow control parameters –…. Conservative version –Pin-to-pin compatibility with sp2b/2c kept: can be used with the existing HBU –SC/Probe registers: no compatibility with the previous versions –Base line : Spiroc2c –Analogue part of CITIROC (variant for CTA): already validated New input 8-bit DAC Preamplifier HG et LG : »independent gains adjustment channel by channel for HG and LG (6 bits) »Switched Cp removed (“rate effect”) »Preamplifier noise reduction by new layout Fabricated in AMS SiGe 0.35 µm Submitted in December 2014 Expected in April 2015 Package in T-QFP 208 Chip area : 32 mm² (4.2mm × 7.2mm) Mardi 16 décembre 2014 - AHCAL main meeting - DESY - Ludovic RAUX 3

4. Bug fix and improvements Many issues already understood and solved in SPIROC 2c will be implemented in SPIROC 2d –Pedestal shift @ huge signals, pedestal different for internal/external trigger. Attributed to long distance cross-talk, corrected by a new layout –Memory cell dependent amplitude decay (“rate effect”). Due to switches on compensation capacitances, removed in 2C/2D –Influence of channel-wise trigger thresholds on the global threshold. Due to internal parasitic resistances, fixed in 2C/2D –Holdscan is different for HG and LG Due to cross-talk between HG and LG –Random zero events and zero-results for the first trigger. Due to ADC management signals sequence, fixed in 2C/2D Mardi 16 décembre 2014 - AHCAL main meeting - DESY - Ludovic RAUX 4

5. Bug fix and improvements “zero event” occurs randomly in Spiroc2b Problem resolved in SPIROC 2c Sequencing of digital control signals No digital part change to be conservative but only a D-flip- flop, a gate on ADC discri and delays on control signals Mardi 16 décembre 2014 - AHCAL main meeting - DESY - Ludovic RAUX 5

6. Bug fix and improvements Modifications on the TDC –To decrease dead time during transition => alternation of a rising and a falling ramp implemented –Conservative modification but not completely satisfying solution –Anyway, a new TDC has to be re- designed in SPIROC 3 (as in PETIROC) Need major change in digital part © Oskar Hartbrich @Wuppertal Mardi 16 décembre 2014 - AHCAL main meeting - DESY - Ludovic RAUX 6

7. New feature in SPIROC2d: Input DAC Input DACs issue: – Input DAC uniformity: performance noticeably improved (difficult due to the small power budget) – Probe on the input DAC – Input DAC reliability: new PAD and 100-Ohm protection resistors Mardi 16 décembre 2014 - AHCAL main meeting - DESY - Ludovic RAUX 7

8. New features in SPIROC 2d Trigger validation by external trigger (testbeam) improved by boosting the “NoTrig” LVDS receivers: The open for « NoTrig » signal should be reduced (from 200ns to 10ns) Power comsumption: no residual current when power off Other minor modifications: 4-bit DAC for trigger level adjustment optimized Bandgap changed : HR3 version used Gain Select & Threshold DACs switched OFF independently LVDS Receivers switched OFF independently “Power on reset” on probe and read register Mardi 16 décembre 2014 - AHCAL main meeting - DESY - Ludovic RAUX 8 Temperature sensor added –Temperature sensor output available on probe or internal ADC New TrigExt policy: Hit bit can be saved

9. Summary Mardi 16 décembre 2014 - AHCAL main meeting - DESY - Ludovic RAUX 9 Many laboratory measurements and testbeam have been done on HARDROC, SKIROC and SPIROC. These measurements allow to understand all the chip features. The feedback from the different users (HBU, EBU, and FEV) and from external users is crucial for us. Submission of SPIROC 2d during our engineering run => intermediate step before switching to 3rd generation chip. This version should correct the weaknesses of the previous versions SPIROC 2d should be an important step towards the final chip.