1. 1 Intel 8086 MICROPROCESSOR ARCHITECTURE

2. 2 Features It is a 16-bit μp. 8086 has a 20 bit address bus can access up to 2 20 memory locations (1 MB). It can support up to 64K I/O ports. It provides 14, 16 -bit registers. Word size is 16 bits and double word size is 4 bytes. It has multiplexed address and data bus AD0- AD15 and A16 – A19.

3. 3 8086 is designed to operate in two modes, Minimum and Maximum. It can prefetches up to 6 instruction bytes from memory and queues them in order to speed up instruction execution. It requires +5V power supply. A 40 pin dual in line package. Address ranges from 00000H to FFFFFH

4. 4 Intel 8086 Internal Architecture

5. 5 Internal architecture of 8086 8086 has two blocks BIU and EU. The BIU handles all transactions of data and addresses on the buses for EU. The BIU performs all bus operations such as instruction fetching, reading and writing operands for memory and calculating the addresses of the memory operands. The instruction bytes are transferred to the instruction queue. EU executes instructions from the instruction system byte queue.

6. 6 BIU contains Instruction queue, Segment registers, Instruction pointer, Address adder. EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index register, Flag register.

7. 7 EXECUTION UNIT Decodes instructions fetched by the BIU Generate control signals, Executes instructions. The main parts are: Control Circuitry Instruction decoder ALU

8. 8 AHAL BHBL CHCL DHDL SP BP SI DI 8 bits 16 bits Accumulator Base Count Data Stack Pointer Base Pointer Source Index Destination Index AX BX CX DX Pointer Index 8 bits 16 bits Accumulator Base Count Data Stack Pointer Base Pointer Source Index Destination Index EXECUTION UNIT – General Purpose Registers

9. 9 RegisterPurpose AXWord multiply, word divide, word I /O ALByte multiply, byte divide, byte I/O, decimal arithmetic AHByte multiply, byte divide BXStore address information CXString operation, loops CLVariable shift and rotate DX Word multiply, word divide, indirect I/O (Used to hold I/O address during I/O instructions. If the result is more than 16-bits, the lower order 16-bits are stored in accumulator and higher order 16-bits are stored in DX register)

10. 10 Pointer And Index Registers used to keep offset addresses. Used in various forms of memory addressing. In the case of SP and BP the default reference to form a physical address is the Stack Segment (SS- will be discussed under the BIU) The index registers (SI & DI) and the BX generally default to the Data segment register (DS). SP: Stack pointer – Used with SS to access the stack segment BP: Base Pointer – Primarily used to access data on the stack – Can be used to access data in other segments

11. 11 SI: Source Index register – is required for some string operations – When string operations are performed, the SI register points to memory locations in the data segment which is addressed by the DS register. Thus, SI is associated with the DS in string operations. DI: Destination Index register – is also required for some string operations. – When string operations are performed, the DI register points to memory locations in the data segment which is addressed by the ES register. Thus, DI is associated with the ES in string operations. The SI and the DI registers may also be used to access data stored in arrays

12. 12 EXECUTION UNIT – Flag Register A flag is a flip flop which indicates some conditions produced by the execution of an instruction or controls certain operations of the EU. In 8086 The EU contains  a 16 bit flag register  9 of the 16 are active flags and remaining 7 are undefined.  6 flags indicates some conditions- status flags  3 flags –control Flags UUUUOFDFIFTFSFZFUAFUPFUCF Carry Over flowDirection Interrupt Trap Sign Zero Auxiliary Parity U - Unused

13. 13 EXECUTION UNIT – Flag Register FlagPurpose Carry (CF)Holds the carry after addition or the borrow after subtraction. Also indicates some error conditions, as dictated by some programs and procedures. Parity (PF)PF=0;odd parity, PF=1;even parity. Auxiliary (AF)Holds the carry (half – carry) after addition or borrow after subtraction between bit positions 3 and 4 of the result (for example, in BCD addition or subtraction.) Zero (ZF)Shows the result of the arithmetic or logic operation. Z=1; result is zero. Z=0; The result is 0 Sign (SF)Holds the sign of the result after an arithmetic/logic instruction execution. S=1; negative, S=0

14. 14 FlagPurpose Trap (TF) A control flag. Enables the trapping through an on-chip debugging feature. Interrupt (IF) A control flag. Controls the operation of the INTR (interrupt request) I=0; INTR pin disabled. I=1; INTR pin enabled. Direction (DF) A control flag. It selects either the increment or decrement mode for DI and /or SI registers during the string instructions. Overflow (OF) Overflow occurs when signed numbers are added or subtracted. An overflow indicates the result has exceeded the capacity of the Machine

15. 15 Execution unit – Flag Register Six of the flags are status indicators reflecting properties of the last arithmetic or logical instruction. For example, if register AL = 7Fh and the instruction ADD AL,1 is executed then the following happen AL = 80h CF = 0; there is no carry out of bit 7 PF = 0; 80h has an odd number of ones AF = 1; there is a carry out of bit 3 into bit 4 ZF = 0; the result is not zero SF = 1; bit seven is one OF = 1; the sign bit has changed

16. 16 BUS INTERFACE UNIT (BIU) Contains 6-byte Instruction Queue (Q) The Segment Registers (CS, DS, ES, SS). The Instruction Pointer (IP). The Address Summing block (Σ)

17. 17 THE QUEUE (Q) The BIU uses a mechanism known as an instruction stream queue to implement a pipeline architecture. This queue permits pre-fetch of up to 6 bytes of instruction code. Whenever the queue of the BIU is not full, it has room for at least two more bytes and at the same time the EU is not requesting it to read or write operands from memory, the BIU is free to look ahead in the program by pre-fetching the next sequential instruction.

18. 18 Segmented Memory Code segment (64KB) Data segment (64KB) Extra segment (64KB) Stack segment (64KB) 1 MB  The memory in an 8086/88 based system is organized as segmented memory.  The CPU 8086 is able to address 1Mbyte of memory.  The Complete physically available memory may be divided into a number of logical segments. 00000 FFFFF Physical Memory

19. 19 The size of each segment is 64 KB A segment may be located any where in the memory Each of these segments can be used for a specific function. –Code segment is used for storing the instructions. –The stack segment is used as a stack and it is used to store the return addresses. –The data and extra segments are used for storing data byte.

20. 20 The 4 segments are Code, Data, Extra and Stack segments. A Segment is a 64kbyte block of memory. The 16 bit contents of the segment registers in the BIU actually point to the starting location of a particular segment. Segments may be overlapped or non-overlapped

21. 21 Segment registers In 8086/88 the processors have 4 segments registers Code Segment register (CS), Data Segment register (DS), Extra Segment register (ES) and Stack Segment (SS) register. All are 16 bit registers. Each of the Segment registers store the upper 16 bit address of the starting address of the corresponding segments.

22. 22 Memory Address Generation Physical Address (20 Bits) Adder Segment Register (16 bits) 0 0 Offset Value (16 bits)

23. 23

24. 24 The following examples shows the CS:IP scheme of address formation: Inserting a hexadecimal 0H (0000B) with the CSR or shifting the CSR four binary digits left 3 4 B A 0 ( C S ) + 8 A B 4 ( I P ) 3 D 6 5 4 (next address) 34BA 8AB4 CS IP 34BA0 3D654 44B9F Code segment 8AB4 (offset)

25. 25 Segment and Address register combination CS:IP SS:SPSS:BP DS:BXDS:SI DS:DI (for other than string operations) ES:DI (for string operations)

26. 26 Summary of Registers & Pipeline of 8086 µP AHAL BHBL CHCL DHDL SP BP SI DI FLAGS DECODERDECODER ALU AX BX CX DXEU Timing control SP BP Default Assignment BIU IP CSDSESSS PIPELINE (or) QUEUE CODEOUTCODEOUT CODEINCODEIN IPBX DI SI DI Fetch & store code bytes in PIPELINE

27. 27

28. Addressing Modes of 8086 Prepared & Presented by- Madhu Oruganti

29. The different ways in which a processor can access data are called addressing modes

30. 8086 accesses code bytes using contents of CS & IP register 8086 accesses stack using contents of SS & SP register

31. How 8086 accesses data? 8086 assembly language instructions can be used to illustrate the addressing modes Format of MOV instruction MOV destination, source

32. Source of data can be –Immediate data –A specified register –A memory location specified in 1 of 24 different ways Destination of data can be –A specified register –A memory location specified in 1 of 24 different ways

33. Classification of Addressing Modes 1.Register addressing mode 2.Immediate addressing mode 3.Memory addressing mode 4.Port addressing mode 5.Relative addressing mode 6.Implied addressing mode

34. 1. Register addressing mode Source/destination can be one of the 8086 registers MOV AX, BX ; 16-bit data transfer MOV AL, BL ; 8-bit data transfer

35. 2. Immediate addressing mode 8 or 16-bit data can be specified as part of the instruction E.g. MOV AL, 45H MOV BX, 5062H

36. 3. Memory addressing mode One of the operands is in memory 8086 must use –a segment register –A 16-bit offset (effective address) By default, DS register is used for accessing data from memory 16-bit offset can be specified in many ways

37. Different ways of specifying offset Direct memory addressing Register Indirect addressing Based addresing Indexed addressing Based Indexed addressing String addressing

38. a. Direct Memory addressing Effective address is specified directly in the instruction E.g. MOV BX, [5062] 20-bit physical address of memory location is calculated using DS and offset value 5062

39. Accessing memory Segment register + = 20-bit physical address of operand 16-bit offset

40. b. Register indirect addressing The effective address of memory operand is present in one of the base or index registers [BX, BP, SI, DI] E.g. MOV CX, [BX] If DS = 2000H, BX = 0004H THEN contents of memory location 20004H are copied to register CX

41. c. Based addressing Effective address is sum of –16-bit offset given in instruction –Contents of base register BX or BP Segment register is DS or SS E.g. MOV AX, 4[BX] E.G. PUSH CX

42. d. Indexed addressing Effective address is sum of –16-bit offset given in instruction –Contents of index register SI or DI Segment register is DS E.g. MOV AX, 4[SI]

43. e. Based Indexed addressing Effective address is sum of –16-bit offset given in instruction –Contents of index register SI or DI –Contents of base register BX or BP Segment register is DS E.g. MOV AX, 4[BX][SI]

44. f. String addressing Used when string related instructions are executed Uses index registers SI register points to the first byte or word of the source string DI register points to the first byte or word of the destination

45. Classification of Addressing Modes 1.Register addressing mode 2.Immediate addressing mode 3.Memory addressing mode 4.Port addressing mode 5.Relative addressing mode 6.Implied addressing mode

46. 4. Port addressing Two I/O port addressing modes can be used –Direct (e.g. IN AL, 02H) –Indirect (e.g. IN AL, DXH)

47. 5. Relative addressing mode Specifies the operand as a 8-bit signed displacement relative to PC E.g. JNC 08H IF carry = 0, THEN PC is loaded with current PC contents + 8-bit signed value

48. 6. Implied addressing mode No operands are specified E.g. CLC Means clear carry flag

49. Instruction Set of 8086 Madhu Oruganti Asst.Prof SNIST HYDERABAD. 2/3/1549oruganti.madhu@gmail.com

50. Instruction Set of 8086 An instruction is a binary pattern designed inside a microprocessor to perform a specific function. The entire group of instructions that a microprocessor supports is called Instruction Set. 8086 has more than 20,000 instructions. 2/3/1550oruganti.madhu@gmail.com

51. Classification of Instruction Set Data Transfer Instructions Arithmetic Instructions Bit Manipulation Instructions Program Execution Transfer Instructions String Instructions Processor Control Instructions 2/3/1551oruganti.madhu@gmail.com

52. Data Transfer Instructions These instructions are used to transfer data from source to destination. The operand can be a constant, memory location, register or I/O port address. 2/3/1552oruganti.madhu@gmail.com

53. Data Transfer Instructions MOV Des, Src: Src operand can be register, memory location or immediate operand. Des can be register or memory operand. Both Src and Des cannot be memory location at the same time. E.g.: MOV CX, 037A H MOV AL, BL MOV BX, [0301 H] 2/3/1553oruganti.madhu@gmail.com

54. Data Transfer Instructions PUSH Operand: It pushes the operand into top of stack. E.g.: PUSH BX POP Des: It pops the operand from top of stack to Des. Des can be a general purpose register, segment register (except CS) or memory location. E.g.: POP AX 2/3/1554 oruganti.madhu@gmail.com

55. Data Transfer Instructions XCHG Des, Src: This instruction exchanges Src with Des. It cannot exchange two memory locations directly. E.g.: XCHG DX, AX 2/3/1555oruganti.madhu@gmail.com

56. Data Transfer Instructions IN Accumulator, Port Address: It transfers the operand from specified port to accumulator register. E.g.: IN AX, 0028 H OUT Port Address, Accumulator: It transfers the operand from accumulator to specified port. E.g.: OUT 0028 H, AX 2/3/1556 oruganti.madhu@gmail.com

57. Data Transfer Instructions LEA Register, Src: It loads a 16-bit register with the offset address of the data specified by the Src. E.g.: LEA BX, [DI] This instruction loads the contents of DI (offset) into the BX register. 2/3/1557oruganti.madhu@gmail.com

58. Data Transfer Instructions LDS Des, Src: It loads 32-bit pointer from memory source to destination register and DS. The offset is placed in the destination register and the segment is placed in DS. To use this instruction the word at the lower memory address must contain the offset and the word at the higher address must contain the segment. E.g.: LDS BX, [0301 H] 2/3/1558oruganti.madhu@gmail.com

59. Data Transfer Instructions LES Des, Src: It loads 32-bit pointer from memory source to destination register and ES. The offset is placed in the destination register and the segment is placed in ES. This instruction is very similar to LDS except that it initializes ES instead of DS. E.g.: LES BX, [0301 H] 2/3/1559oruganti.madhu@gmail.com

60. Data Transfer Instructions LAHF: It copies the lower byte of flag register to AH. SAHF: It copies the contents of AH to lower byte of flag register. PUSHF: Pushes flag register to top of stack. POPF: Pops the stack top to flag register. 2/3/1560oruganti.madhu@gmail.com

61. Arithmetic Instructions ADD Des, Src: It adds a byte to byte or a word to word. It effects AF, CF, OF, PF, SF, ZF flags. E.g.: ADD AL, 74H ADD DX, AX ADD AX, [BX] 2/3/1561oruganti.madhu@gmail.com

62. Arithmetic Instructions ADC Des, Src: It adds the two operands with CF. It effects AF, CF, OF, PF, SF, ZF flags. E.g.: ADC AL, 74H ADC DX, AX ADC AX, [BX] 2/3/1562oruganti.madhu@gmail.com

63. Arithmetic Instructions SUB Des, Src: It subtracts a byte from byte or a word from word. It effects AF, CF, OF, PF, SF, ZF flags. For subtraction, CF acts as borrow flag. E.g.: SUB AL, 74H SUB DX, AX SUB AX, [BX] 2/3/1563oruganti.madhu@gmail.com

64. Arithmetic Instructions SBB Des, Src: It subtracts the two operands and also the borrow from the result. It effects AF, CF, OF, PF, SF, ZF flags. E.g.: SBB AL, 74H SBB DX, AX SBB AX, [BX] 2/3/1564oruganti.madhu@gmail.com

65. Arithmetic Instructions INC Src: It increments the byte or word by one. The operand can be a register or memory location. It effects AF, OF, PF, SF, ZF flags. CF is not effected. E.g.: INC AX 2/3/1565oruganti.madhu@gmail.com

66. Arithmetic Instructions DEC Src: It decrements the byte or word by one. The operand can be a register or memory location. It effects AF, OF, PF, SF, ZF flags. CF is not effected. E.g.: DEC AX 2/3/1566oruganti.madhu@gmail.com

67. Arithmetic Instructions AAA (ASCII Adjust after Addition): The data entered from the terminal is in ASCII format. In ASCII, 0 – 9 are represented by 30H – 39H. This instruction allows us to add the ASCII codes. This instruction does not have any operand. Other ASCII Instructions: AAS (ASCII Adjust after Subtraction) AAM (ASCII Adjust after Multiplication) AAD (ASCII Adjust Before Division) 2/3/1567oruganti.madhu@gmail.com

68. Arithmetic Instructions DAA (Decimal Adjust after Addition) It is used to make sure that the result of adding two BCD numbers is adjusted to be a correct BCD number. It only works on AL register. DAS (Decimal Adjust after Subtraction) It is used to make sure that the result of subtracting two BCD numbers is adjusted to be a correct BCD number. It only works on AL register. 2/3/1568oruganti.madhu@gmail.com

69. Arithmetic Instructions NEG Src: It creates 2’s complement of a given number. That means, it changes the sign of a number. 2/3/1569oruganti.madhu@gmail.com

70. Arithmetic Instructions CMP Des, Src: It compares two specified bytes or words. The Src and Des can be a constant, register or memory location. Both operands cannot be a memory location at the same time. The comparison is done simply by internally subtracting the source from destination. The value of source and destination does not change, but the flags are modified to indicate the result. 2/3/1570oruganti.madhu@gmail.com

71. Arithmetic Instructions MUL Src: It is an unsigned multiplication instruction. It multiplies two bytes to produce a word or two words to produce a double word. AX = AL * Src DX : AX = AX * Src This instruction assumes one of the operand in AL or AX. Src can be a register or memory location. IMUL Src: It is a signed multiplication instruction. 2/3/1571oruganti.madhu@gmail.com

72. Arithmetic Instructions DIV Src: It is an unsigned division instruction. It divides word by byte or double word by word. The operand is stored in AX, divisor is Src and the result is stored as: AH = remainderAL = quotient IDIV Src: It is a signed division instruction. 2/3/1572oruganti.madhu@gmail.com

73. Arithmetic Instructions CBW (Convert Byte to Word): This instruction converts byte in AL to word in AX. The conversion is done by extending the sign bit of AL throughout AH. CWD (Convert Word to Double Word): This instruction converts word in AX to double word in DX : AX. The conversion is done by extending the sign bit of AX throughout DX. 2/3/1573oruganti.madhu@gmail.com

74. Bit Manipulation Instructions These instructions are used at the bit level. These instructions can be used for: Testing a zero bit Set or reset a bit Shift bits across registers 2/3/1574oruganti.madhu@gmail.com

75. Bit Manipulation Instructions NOT Src: It complements each bit of Src to produce 1’s complement of the specified operand. The operand can be a register or memory location. 2/3/1575oruganti.madhu@gmail.com

76. Bit Manipulation Instructions AND Des, Src: It performs AND operation of Des and Src. Src can be immediate number, register or memory location. Des can be register or memory location. Both operands cannot be memory locations at the same time. CF and OF become zero after the operation. PF, SF and ZF are updated. 2/3/1576oruganti.madhu@gmail.com

77. Bit Manipulation Instructions OR Des, Src: It performs OR operation of Des and Src. Src can be immediate number, register or memory location. Des can be register or memory location. Both operands cannot be memory locations at the same time. CF and OF become zero after the operation. PF, SF and ZF are updated. 2/3/1577oruganti.madhu@gmail.com

78. Bit Manipulation Instructions XOR Des, Src: It performs XOR operation of Des and Src. Src can be immediate number, register or memory location. Des can be register or memory location. Both operands cannot be memory locations at the same time. CF and OF become zero after the operation. PF, SF and ZF are updated. 2/3/1578oruganti.madhu@gmail.com

79. Bit Manipulation Instructions SHL Des, Count: It shift bits of byte or word left, by count. It puts zero(s) in LSBs. MSB is shifted into carry flag. If the number of bits desired to be shifted is 1, then the immediate number 1 can be written in Count. However, if the number of bits to be shifted is more than 1, then the count is put in CL register. 2/3/1579oruganti.madhu@gmail.com

80. Bit Manipulation Instructions SHR Des, Count: It shift bits of byte or word right, by count. It puts zero(s) in MSBs. LSB is shifted into carry flag. If the number of bits desired to be shifted is 1, then the immediate number 1 can be written in Count. However, if the number of bits to be shifted is more than 1, then the count is put in CL register. 2/3/1580oruganti.madhu@gmail.com

81. Bit Manipulation Instructions ROL Des, Count: It rotates bits of byte or word left, by count. MSB is transferred to LSB and also to CF. If the number of bits desired to be shifted is 1, then the immediate number 1 can be written in Count. However, if the number of bits to be shifted is more than 1, then the count is put in CL register. 2/3/1581oruganti.madhu@gmail.com

82. Bit Manipulation Instructions ROR Des, Count: It rotates bits of byte or word right, by count. LSB is transferred to MSB and also to CF. If the number of bits desired to be shifted is 1, then the immediate number 1 can be written in Count. However, if the number of bits to be shifted is more than 1, then the count is put in CL register. 2/3/1582oruganti.madhu@gmail.com

83. Program Execution Transfer Instructions These instructions cause change in the sequence of the execution of instruction. This change can be through a condition or sometimes unconditional. The conditions are represented by flags. 2/3/1583oruganti.madhu@gmail.com

84. Program Execution Transfer Instructions CALL Des: This instruction is used to call a subroutine or function or procedure. The address of next instruction after CALL is saved onto stack. RET: It returns the control from procedure to calling program. Every CALL instruction should have a RET. 2/3/1584oruganti.madhu@gmail.com

85. Program Execution Transfer Instructions JMP Des: This instruction is used for unconditional jump from one place to another. Jxx Des (Conditional Jump): All the conditional jumps follow some conditional statements or any instruction that affects the flag. 2/3/1585oruganti.madhu@gmail.com

86. Conditional Jump Table MnemonicMeaningJump Condition JAJump if AboveCF = 0 and ZF = 0 JAEJump if Above or EqualCF = 0 JBJump if BelowCF = 1 JBEJump if Below or EqualCF = 1 or ZF = 1 JCJump if CarryCF = 1 JEJump if EqualZF = 1 JNCJump if Not CarryCF = 0 JNEJump if Not EqualZF = 0 JNZJump if Not ZeroZF = 0 JPEJump if Parity EvenPF = 1 JPOJump if Parity OddPF = 0 JZJump if ZeroZF = 1 2/3/1586oruganti.madhu@gmail.com

87. Program Execution Transfer Instructions Loop Des: This is a looping instruction. The number of times looping is required is placed in the CX register. With each iteration, the contents of CX are decremented. ZF is checked whether to loop again or not. 2/3/1587oruganti.madhu@gmail.com

88. String Instructions String in assembly language is just a sequentially stored bytes or words. There are very strong set of string instructions in 8086. By using these string instructions, the size of the program is considerably reduced. 2/3/1588oruganti.madhu@gmail.com

89. String Instructions CMPS Des, Src: It compares the string bytes or words. SCAS String: It scans a string. It compares the String with byte in AL or with word in AX. 2/3/1589oruganti.madhu@gmail.com

90. String Instructions MOVS / MOVSB / MOVSW: It causes moving of byte or word from one string to another. In this instruction, the source string is in Data Segment and destination string is in Extra Segment. SI and DI store the offset values for source and destination index. 2/3/1590oruganti.madhu@gmail.com

91. String Instructions REP (Repeat): This is an instruction prefix. It causes the repetition of the instruction until CX becomes zero. E.g.: REP MOVSB STR1, STR2 It copies byte by byte contents. REP repeats the operation MOVSB until CX becomes zero. 2/3/1591oruganti.madhu@gmail.com

92. Processor Control Instructions These instructions control the processor itself. 8086 allows to control certain control flags that: causes the processing in a certain direction processor synchronization if more than one microprocessor attached. 2/3/1592oruganti.madhu@gmail.com

93. Processor Control Instructions STC: It sets the carry flag to 1. CLC: It clears the carry flag to 0. CMC: It complements the carry flag. 2/3/1593oruganti.madhu@gmail.com

94. Processor Control Instructions STD: It sets the direction flag to 1. If it is set, string bytes are accessed from higher memory address to lower memory address. CLD: It clears the direction flag to 0. If it is reset, the string bytes are accessed from lower memory address to higher memory address. 2/3/1594oruganti.madhu@gmail.com

95. Thank You Have a Nice Day 952/3/15oruganti.madhu@g mail.com