1. CPE432 Chapter 4B.1Dr. W. Abu-Sufah, UJ Chapter 4B: The Processor, Part B-1 Read Sections 4.7 Adapted from Slides by Prof. Mary Jane Irwin, Penn State University And Slides Supplied by the textbook publisher

2. CPE432 Chapter 4B.2Dr. W. Abu-Sufah, UJ Review: Why Pipeline? For Performance! I n s t r. O r d e r Time (clock cycles) Inst 0 Inst 1 Inst 2 Inst 4 Inst 3 ALU IM Reg DMReg ALU IM Reg DMReg ALU IM Reg DMReg ALU IM Reg DMReg ALU IM Reg DMReg Once the pipeline is full, one instruction is completed every cycle, so CPI = 1 Time to fill the pipeline CC0CC1CC2CC3CC4 CC5 CC6CC7CC8

3. CPE432 Chapter 4B.3Dr. W. Abu-Sufah, UJ Review: MIPS Pipeline Data and Control Paths Read Address Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 1632 ALU Shift left 2 Add Data Memory Address Write Data Read Data IF/ID Sign Extend ID/EX EX/MEM MEM/WB Control ALU cntrl RegWrite MemWriteMemRead MemtoReg RegDst ALUOp ALUSrc Branch PCSrc How many bits wide is each pipeline register?

4. CPE432 Chapter 4B.4Dr. W. Abu-Sufah, UJ Review: Can Pipelining Get Us Into Trouble?  Yes: Pipeline Hazards l structural hazards: attempt to use the same resource by two different instructions at the same time l data hazards: attempt to use data before it is ready -An instruction’s source operand(s) are produced by a prior instruction still in the pipeline l control hazards: attempt to make a decision about program control flow before the branch condition has been evaluated and the new PC target address calculated -branch and jump instructions, exceptions  Pipeline control must detect the hazard and then take action to resolve hazards

5. CPE432 Chapter 4B.5Dr. W. Abu-Sufah, UJ Review: Register Usage Can Cause Data Hazards ALU IM Reg DMReg ALU IM Reg DMReg ALU IM Reg DMReg ALU IM Reg DMReg ALU IM Reg DMReg  “Read before Write” data hazard add $1,$2,$3 sub $4,$1,$5 and $6,$7,$1 xor $4,$1,$5 or $8,$1,$9 Value of $1 10 10 10 10 10/-20 -20 -20 -20 -20 CC0CC1CC2CC3CC4 CC5 CC6CC7CC8

6. CPE432 Chapter 4B.6Dr. W. Abu-Sufah, UJ stall One Way to “Fix” a Data Hazard I n s t r. O r d e r add $1, ALU IM Reg DMReg sub $4,$1,$5 and $6,$7,$1 ALU IM Reg DMReg ALU IM Reg DMReg Can fix data hazard by waiting – stall – but this increases CPI CC0CC1CC2CC3CC4 CC5 CC6CC7CC8 Value of $1 10 10 10 10 10/-20 -20 -20 -20 -20

7. CPE432 Chapter 4B.7Dr. W. Abu-Sufah, UJ Another Way to “Fix” a Data Hazard ALU IM Reg DMReg ALU IM Reg DMReg ALU IM Reg DMReg Fix data hazards by forwarding results when they are needed from where they are available ALU IM Reg DMReg ALU IM Reg DMReg I n s t r. O r d e r add $1, sub $4,$1,$5 and $6,$7,$1 xor $4,$1,$5 or $8,$1,$9 CC0CC1CC2CC3CC4 CC5 CC6CC7CC8 Result of the “ instruction is available at the end of CC2 in the EX/MEM register and at the end of CC3 in the MEM/WB register “add $1,”

8. CPE432 Chapter 4B.8Dr. W. Abu-Sufah, UJ Data Forwarding {aka Bypassing}  During a clock cycle, take the result from any of the pipeline state registers where it is stored and forward it to the functional units (e.g., the ALU) that needs it in that cycle  For ALU functional unit: the inputs can come from EX/MEM or MEM/WB pipeline registers rather than just from ID/EX pipeline register l add multiplexors to the inputs of the ALU l connect the “rd” write data in EX/MEM or MEM/WB to both of the EX’s stage “rs” and “rt” ALU mux inputs l add the proper control hardware to control the new muxes  Other functional units may need similar forwarding logic (e.g., the DM)  With forwarding we can achieve a CPI of 1 even in the presence of data dependencies

9. CPE432 Chapter 4B.9Dr. W. Abu-Sufah, UJ Data Forwarding Control Conditions 1.EX Forward Unit: if { EX/MEM.RegWrite and (EX/MEM.RegisterRd != 0) and (EX/MEM.RegisterRd = ID/EX.RegisterRs) } ForwardA = 10 if { EX/MEM.RegWrite and (EX/MEM.RegisterRd != 0) and (EX/MEM.RegisterRd = ID/EX.RegisterRt) } ForwardB = 10 Forwards the result from the previous instr. to either input of the ALU Forwards the result from the second previous instr. to either input of the ALU 2.MEM Forward Unit: if { MEM/WB.RegWrite and (MEM/WB.RegisterRd != 0) and (MEM/WB.RegisterRd = ID/EX.RegisterRs) } ForwardA = 01 if { MEM/WB.RegWrite and (MEM/WB.RegisterRd != 0) and (MEM/WB.RegisterRd = ID/EX.RegisterRt) } ForwardB = 01

10. CPE432 Chapter 4B.10Dr. W. Abu-Sufah, UJ Forwarding Illustration I n s t r. O r d e r add $1, sub $4,$1,$5 and $6,$7,$1 ALU IM Reg DMReg ALU IM Reg DMReg ALU IM Reg DMReg EX forwardingMEM forwarding

11. CPE432 Chapter 4B.11Dr. W. Abu-Sufah, UJ Yet Another Complication! I n s t r. O r d e r add $1,$1,$2 ALU IM Reg DMReg add $1,$1,$3 add $1,$1,$4 ALU IM Reg DMReg ALU IM Reg DMReg  Another potential data hazard can occur when there is a conflict between the result of the WB stage instruction and the MEM stage instruction – which should be forwarded?

12. CPE432 Chapter 4B.12Dr. W. Abu-Sufah, UJ Yet Another Complication! I n s t r. O r d e r add $1,$1,$2 ALU IM Reg DMReg add $1,$1,$3 add $1,$1,$4 ALU IM Reg DMReg ALU IM Reg DMReg  Another potential data hazard can occur when there is a conflict between the result of the WB stage instruction and the MEM stage instruction – which should be forwarded?

13. CPE432 Chapter 4B.13Dr. W. Abu-Sufah, UJ Corrected Data Forwarding Control Conditions 2.MEM Forward Unit: if (MEM/WB.RegWrite and (MEM/WB.RegisterRd != 0) and (EX/MEM.RegisterRd != ID/EX.RegisterRs) and (MEM/WB.RegisterRd = ID/EX.RegisterRs)) ForwardA = 01 if (MEM/WB.RegWrite and (MEM/WB.RegisterRd != 0) and (EX/MEM.RegisterRd != ID/EX.RegisterRt) and (MEM/WB.RegisterRd = ID/EX.RegisterRt)) ForwardB = 01 1.EX Forward Unit: if (EX/MEM.RegWrite and (EX/MEM.RegisterRd != 0) and (EX/MEM.RegisterRd = ID/EX.RegisterRs)) ForwardA = 10 if (EX/MEM.RegWrite and (EX/MEM.RegisterRd != 0) and (EX/MEM.RegisterRd = ID/EX.RegisterRt)) ForwardB = 10 Forwards the result from the previous instr. to either input of the ALU Forwards the result from second previous instr. to either input of the ALU (provided result is not available from the previous instr)

14. CPE432 Chapter 4B.14Dr. W. Abu-Sufah, UJ Datapath with Forwarding Hardware PCSrc Read Address Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 1632 ALU Shift left 2 Add Data Memory Address Write Data Read Data IF/ID Sign Extend ID/EX EX/MEM MEM/WB Control ALU cntrl Branch Forward Unit

15. CPE432 Chapter 4B.15Dr. W. Abu-Sufah, UJ Datapath with Forwarding Hardware PCSrc ID/EX.RegisterRt ID/EX.RegisterRs EX/MEM.RegisterRd MEM/WB.RegisterRd EX/MEM.RegWrite MEM/WB.RegWrite How many bits wide is each pipeline register now?