1. EEM 486: Computer Architecture Lecture 3 Designing Single Cycle Control

2. Lec 3.2 The Big Picture: Where are We Now? Control Datapath Memory Processor Input Output

3. Lec 3.3 An Abstract View of the Implementation Data Out Clk 5 RwRaRb 32 32-bit Registers Rd ALU Clk Data In Data Address Ideal Data Memory Instruction Address Ideal Instruction Memory Clk PC 5 Rs 5 Rt 32 A B Next Address Control Datapath Control Signals Conditions

4. Lec 3.4 Recap: A Single Cycle Datapath  We have everything except control signals (underline)

5. Lec 3.5 Recap: Meaning of the Control Signals  nPC_MUX_sel: 0  PC <– PC + 4 1  PC <– PC + 4 + SignExt(Im16) || 00 Adr Inst Memory Adder PC Clk 00 Mux 4 nPC_MUX_sel PC Ext imm16

6. Lec 3.6 Recap: Meaning of the Control Signals  ExtOp: “zero”, “sign”  ALUsrc: 0  regB; 1  immed  ALUctr: “add”, “sub”, “or”  MemWr:1  write memory  MemtoReg:0  ALU; 1  Mem  RegDst:0  “rt”; 1  “rd”  RegWr:1  write register

7. Lec 3.7 RTL: The Add Instruction  addrd, rs, rt mem[PC]Fetch the instruction from memory R[rd] <- R[rs] + R[rt]The actual operation PC <- PC + 4Calculate the next instruction’s address oprsrtrdshamtfunct 061116212631 6 bits 5 bits

8. Lec 3.8 Instruction Fetch Unit at the Beginning of Add  Fetch the instruction from Instruction memory: Instruction <- mem[PC]  Same for all instructions Adr Inst Memory Adder PC Clk 00 Mux 4 nPC_MUX_sel imm16 Instruction 0 1

9. Lec 3.9 The Single Cycle Datapath During Add  R[rd] <- R[rs] + R[rt]

10. Lec 3.10 Instruction Fetch Unit at the End of Add  PC <- PC + 4 This is the same for all instructions except: Branch and Jump Adr Inst Memory Adder PC Clk 00 Mux 4 nPC_MUX_sel imm16 Instruction 0 1

11. Lec 3.11 The Single Cycle Datapath During Or Immediate  R[rt] <- R[rs] or ZeroExt[Imm16] RegDst =

12. Lec 3.12 The Single Cycle Datapath During Or Immediate

13. Lec 3.13 The Single Cycle Datapath During Load  R[rt] <- Data Memory [ R[rs] + SignExt[imm16] ]

14. Lec 3.14 The Single Cycle Datapath During Store  Data Memory [ R[rs] + SignExt[imm16] ] <- R[rt]

15. Lec 3.15 The Single Cycle Datapath During Store

16. Lec 3.16 The Single Cycle Datapath During Branch  if (R[rs] - R[rt] == 0) then Zero <- 1 ; else Zero <- 0

17. Lec 3.17 Instruction Fetch Unit at the End of Branch  What is encoding of nPC_sel? Direct MUX select? Branch / not branch Instruction nPC_sel Adr Inst Memory Adder PC Clk 00 Mux 4 imm16 0 1 Zero nPC_MUX_sel

18. Lec 3.18 Step 4: Given Datapath: RTL -> Control ALUctr RegDstALUSrcExtOpMemtoRegMemWr Zero Instruction Imm16RdRsRt nPC_sel Adr Inst Memory DATA PATH Control Op Fun RegWr

19. Lec 3.19 Summary of Control Signals inst Register Transfer ADDR[rd] <– R[rs] + R[rt];PC <– PC + 4 ALUsrc = RegB, ALUctr = “add”, RegDst = rd, RegWr, nPC_sel = “+4” SUBR[rd] <– R[rs] – R[rt];PC <– PC + 4 ALUsrc = RegB, ALUctr = “sub”, RegDst = rd, RegWr, nPC_sel = “+4” ORiR[rt] <– R[rs] + zero_ext(Imm16); PC <– PC + 4 ALUsrc = Im, Extop = “Z”, ALUctr = “or”, RegDst = rt, RegWr, nPC_sel = “+4” LOADR[rt] <– MEM[ R[rs] + sign_ext(Imm16)];PC <– PC + 4 ALUsrc = Im, Extop = “Sn”, ALUctr = “add”, MemtoReg, RegDst = rt, RegWr, nPC_sel = “+4” STOREMEM[ R[rs] + sign_ext(Imm16)] <– R[rt];PC <– PC + 4 ALUsrc = Im, Extop = “Sn”, ALUctr = “add”, MemWr, nPC_sel = “+4” BEQif ( R[rs] == R[rt] ) then PC <– [PC + sign_ext(Imm16)] || 00 else PC <– PC + 4 nPC_sel = “Br”, ALUctr = “sub”

20. Lec 3.20 Summary of the Control Signals

21. Lec 3.21 Concept of Local Decoding Main Control op 6 ALU Control (Local) func N 6 ALUop ALUctr 3 ALU R-typeorilwswbeq RegDst ALUSrc MemtoReg RegWrite MemWrite Branch ExtO p ALUop 1 0 0 1 0 0 x “R-type” 0 1 0 1 0 0 0 Or 0 1 1 1 0 0 1 Add x 1 x 0 1 0 1 x 0 x 0 0 1 x Sub op00 0000 00 110110 001110 101100 0100

22. Lec 3.22 Encoding of ALUop  In this exercise, ALUop has to be 2 bits wide to represent: (1) “R-type” instructions “I-type” instructions that require the ALU to perform: -(2) Or, (3) Add, and (4) Subtract  To implement the full MIPS ISA, ALUop has to be 3 bits to represent: (1) “R-type” instructions “I-type” instructions that require the ALU to perform: -(2) Or, (3) Add, (4) Subtract, (5) And, and (6) Xor Main Control op 6 ALU Control (Local) func N 6 ALUop ALUctr 3 R-typeorilwswbeq ALUop (Symbolic)“R-type”OrAdd Sub ALUop 1 000 100 00 0 01

23. Lec 3.23 Decoding of the “func” Field Main Control op 6 ALU Control (Local) func N 6 ALUop ALUctr 3 oprsrtrdshamtfunct 061116212631 R-type funct Instruction Operation 10 0000 10 0010 10 0100 10 0101 10 1010 add subtract and or set-on-less-than ALUctr ALU Operation 000 001 010 110 111 And Or Add Subtract Set-on-less-than ALUctr ALU R-typeorilwswbeq ALUop (Symbolic)“R-type”OrAdd Sub ALUop 1 000 100 00 0 01

24. Lec 3.24 Truth Table for ALUctr R-typeorilwswbeq ALUop (Symbolic) “R-type”OrAdd Sub ALUop 1 000 100 00 0 01 funct Instruction Op. 0000 0010 0100 0101 1010 add subtract and or set-on-less-than

25. Lec 3.25 Logic Equation for ALUctr ALUctr = !ALUop & ALUop + ALUop & !func & func & !func ALUopfunc bit ALUctr 0x1xxxx1 1xx00101 1xx10101 This makes func a don’t care

26. Lec 3.26 Logic Equation for ALUctr ALUopfunc bit 000xxxx1 ALUctr 0x1xxxx1 1xx00001 1xx00101 1xx10101 ALUctr = !ALUop & !ALUop + !ALUop & ALUop + ALUop & !func & !func

27. Lec 3.27 Logic Equation for ALUctr ALUopfunc bit ALUctr 01xxxxx1 1xx01011 1xx10101 ALUctr = !ALUop & ALUop + ALUop & !func & func & !func & func + ALUop & func & !func & func & !func

28. Lec 3.28 ALU Control Block ALU Control (Local) func 3 6 ALUop ALUctr 3 ALUctr = !ALUop & ALUop + ALUop & !func & func & !func ALUctr = !ALUop & !ALUop + !ALUop & ALUop ALUop & !func & !func ALUctr = !ALUop & ALUop + ALUop & !func & func & !func & func + ALUop & func & !func & func & !func

29. Lec 3.29 Step 5: Logic For Each Control Signal  nPC_sel <= if (OP == BEQ) then “Br” else “+4”  ALUsrc <=if (OP == “Rtype”) then “regB” else “immed”  ALUctr<= if (OP == “Rtype”) then funct elseif (OP == ORi) then “OR” elseif (OP == BEQ) then “sub” else “add”  ExtOp <= _____________  MemWr<= _____________  MemtoReg<= _____________  RegWr:<=_____________  RegDst:<= _____________

30. Lec 3.30 Step 5: Logic for Each Control Signal  nPC_sel <= if (OP == BEQ) then “Br” else “+4”  ALUsrc <=if (OP == “Rtype”) then “regB” else “immed”  ALUctr<= if (OP == “Rtype”) then funct elseif (OP == ORi) then “OR” elseif (OP == BEQ) then “sub” else “add”  ExtOp <= if (OP == ORi) then “zero” else “sign”  MemWr<= (OP == Store)  MemtoReg<= (OP == Load)  RegWr:<= if ((OP == Store) || (OP == BEQ)) then 0 else 1  RegDst:<= if ((OP == Load) || (OP == ORi)) then 0 else 1

31. Lec 3.31 “Truth Table” for the Main Control Main Control op 6 ALU Control (Local) func 3 6 ALUop ALUctr 3 RegDst ALUSrc :

32. Lec 3.32 “Truth Table” for RegWrite RegWrite = R-type + ori + lw = !op & !op & !op & !op & !op & !op (R-type) + !op & !op & op & op & !op & op (ori) + op & !op & !op & !op & op & op (lw) R-typeorilwswbeq RegWrite11100 op00 0000 00 110110 001110 101100 0100

33. Lec 3.33 PLA Implementation of the Main Control.....

34. Lec 3.34 Putting it All Together: A Single Cycle Processor

35. Lec 3.35 Recap: An Abstract View of the Critical Path (Load) Critical Path (Load Operation) = PC’s Clk-to-Q + Instruction Memory’s Access Time + Register File’s Access Time + ALU to Perform a 32-bit Add + Data Memory Access Time + Setup Time for Register File Write + Clock Skew Clk 5 RwRaRb 32 32-bit Registers Rd ALU Clk Data In Data Address Ideal Data Memory Instruction Address Ideal Instruction Memory Clk PC 5 Rs 5 Rt 16 Imm 32 A B Next Address

36. Lec 3.36 Worst Case Timing (Load) Clk PC Rs, Rt, Rd, Op, Func Clk-to-Q ALUctr Instruction Memory Access Time Old ValueNew Value RegWrOld ValueNew Value Delay through Control Logic busA Register File Access Time Old ValueNew Value busB ALU Delay Old ValueNew Value Old ValueNew Value Old Value ExtOpOld ValueNew Value ALUSrcOld ValueNew Value MemtoRegOld ValueNew Value AddressOld ValueNew Value busWOld ValueNew Delay through Extender & Mux Register Write Occurs Data Memory Access Time

37. Lec 3.37 Drawback of this Single Cycle Processor  Long cycle time: Cycle time must be long enough for the load instruction: PC’s Clock -to-Q + Instruction Memory Access Time + Register File Access Time + ALU Delay (address calculation) + Data Memory Access Time + Register File Setup Time + Clock Skew  Cycle time for load is much longer than needed for all other instructions

38. Lec 3.38  Single cycle datapath => CPI=1, CCT => long  5 steps to design a processor 1. Analyze instruction set => datapath requirements 2. Select set of datapath components & establish clock methodology 3. Assemble datapath meeting the requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic  Control is the hard part  MIPS makes control easier Instructions same size Source registers always in same place Immediates same size, location Operations always on registers/immediates Summary Control Datapath Memory Processor Input Output