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Ken Wyllie, CERN Tracker ASIC, 5th July 2012 1 Overview of LHCb Upgrade Electronics Thanks for the invitation to Krakow!

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Presentation on theme: "Ken Wyllie, CERN Tracker ASIC, 5th July 2012 1 Overview of LHCb Upgrade Electronics Thanks for the invitation to Krakow!"— Presentation transcript:

1 Ken Wyllie, CERN Tracker ASIC, 5th July 2012 1 Overview of LHCb Upgrade Electronics Thanks for the invitation to Krakow!

2 Ken Wyllie, CERN Tracker ASIC, 5th July 2012 2Ken Wyllie, CERN CBM Workshop, January 2012 2 Electronics architecture Ken Wyllie, CERN ACES, March 9th 2011 2 HLT Current HLT++ Upgrade 1MHz event rate 40MHz event rate Readout Supervisor L0 Hardware Trigger Readout Supervisor Low-level Trigger Front-end electronics: transmit data from every 25ns BX

3 Ken Wyllie, CERN Tracker ASIC, 5th July 2012 3 Typical Implementation TELL 40 TELL ECS/TFC

4 Ken Wyllie, CERN Tracker ASIC, 5th July 2012 4 Zoom on Implementation

5 Ken Wyllie, CERN Tracker ASIC, 5th July 2012 5 Reminder of FE specifications LHCb note http://cdsweb.cern.ch/record/1340939/files/LHCb-PUB-2011-011.pdf TFC note http://cdsweb.cern.ch/record/1424363/files/LHCb-PUB-2012-001.pdf Both notes list requirements that must be satisfied by front-end chips! Examples: Bunch counter Resets Non-zero suppressed mode Etc etc etc

6 Ken Wyllie, CERN Tracker ASIC, 5th July 2012 6 Interfaces on FE ASIC GBT Eports for data: SLVS @ 80, 160, or 320 Mb/s Each has input, output, clock Phased clocks (8):SLVS, each can be 40, 80, 160 or 320 MHz GBT-SCA Single-ended CMOS (1.2-2.5V compatible) I2C is the favourite protocol Timing/Fast Control (from GBTX) SLVS bus of maximum 24 bits Power Rad-tol DC-DC convertors are best option Are linear regulators needed in ASIC?

7 Ken Wyllie, CERN Tracker ASIC, 5th July 2012 7 Reviews 1.Conceptual Design Review (part of system review) Chip architecture, functions, compatible with system, happy clients 2. Design Review 3.Production Readiness Review WHEN ???????

8 Ken Wyllie, CERN Tracker ASIC, 5th July 2012 8 General comments Try to share (eg ATLAS):voltage regulator? bandgap Borrow blocks: Eport from GBT i2c slave PLL …….. Simulations of detector occupancy Good Monte Carlo at L = 2 x 10 33 Where are bottle-necks in design? What safety margin? Testability + features for detector commissioning Hybrid design? Should run in parallel with ASIC design

9 Ken Wyllie, CERN Tracker ASIC, 5th July 2012 9 Next meeting 26 th July, general electronics meeting followed by session dedicated to Tracker Electronics issues http://lhcb-elec.web.cern.ch/lhcb-elec/html/upgrade.htm Mailing list: Go to simba.cern.ch, search for lhcb-upgrade-electronics


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