1. CAD for VLSI Ramakrishna sramki@gmail.com Lecture#2

2. © Ramakrishna2 Lecture#2 Outline Hardware Modeling Reference G DeMicheli “Synthesis and Optimization of Digital Circuits” – Ch3 General literature

3. © Ramakrishna3 Typical Synthesis Output int main( void ){ … for( i = 0; i < 8; ++i ) { for( j = 0; j < 8; ++j ) { /* Computation */ } … } /* main() */ Controller Datapath

4. © Ramakrishna4 Design Flow and CAD

5. © Ramakrishna5 Hardware Modeling Abstraction Shows relevant features without associated details. It is easy to reason their properties. Easy to handle. Modeling differs depending on the abstraction level E.g. Architectural, logic, geometric Behavioral, structural, physical Language, diagram, mathematical model

6. © Ramakrishna6 Gajski’s Y-chart

7. © Ramakrishna7 Abstraction for Modeling

8. © Ramakrishna8 Structural Modeling The system structure is a collection of interconnected components, that are recursively divided into sub- components. Cells, Entities, blocks, modules, macros elements ….. These are one and the same:

9. © Ramakrishna9 Control Intensive Designs < X- > X+ J J C1 C2 C1 = 0, C2 = 0 reduction C1 = 0, C2 = 1 no reduction C1 = 1, C2 = 0 no reduction C1 = 1, C2 = 1 reduction 0 0 1 1 Clock On Legend Cx = Conditional Statements J = Join

10. © Ramakrishna10 for( v = 0; v < N; ++v ) { for( i = 0; i < N; ++i ) { temp = 0.0; for( j = 0; j < M; ++j ) { temp += (Coeff[i][j] * Input[v][j]); } DCT1D_Result[v][i] = temp;} }

11. © Ramakrishna11 The Algorithm Head Tail Set 1: All Vertices Reachable from Head (BLACK) Run DFS from Tail Set2 : All the Vertices Reachable from Tail Reverse the graph (copy) Run Depth First Search (DFS) from Head

12. © Ramakrishna12 The Algorithm Head Set 1: All Vertices Reachable from Head (BLACK) Tail Run DFS from Tail Set2 : All the Vertices Reachable from Tail (Tan) Intersect 2 Sets Reverse the graph (copy) Run Depth First Search (DFS) from Head

13. © Ramakrishna13 Outermost nesting Entry Point 2 nd level nesting entry point 3rd level nesting entry point 4th level nesting entry point Exit Point 4 Exit Point 3 Exit Point 2 Outermost Exit Point

14. © Ramakrishna14 Outermost nesting Entry Point 2 nd level nesting entry point 3rd level nesting entry point 4th level nesting entry point Exit Point 4 Exit Point 3 Exit Point 2 Outermost Exit Point

15. © Ramakrishna15 Outermost nesting Entry Point 2 nd level nesting entry point 3rd level nesting entry point 4th level nesting entry point Exit Point 4 Exit Point 3 Exit Point 2 Outermost Exit Point

16. © Ramakrishna16 Algorithmic Details 1.Identify Loops and their sizes (Partition1) 2.Find out registers being shared among them 3.Use Profiling Data to group “things” along the most frequent pathsUse Profiling Data to group “things” along the most frequent paths things = operators, registers 4.Mutual exclusiveness for Resource Sharing (Scheduler’s headache actually) 5.Memory Accesses.

17. © Ramakrishna17 Cost Function Multi Valued CF being considered for partitioning. Regression based analysis will give better CF, but iterations Vs granularity traded for the CF. Metrics: –Latency Latency termed in control steps rather than the actual scale/clock. Min latency is calculated before partitioning by using the profiling information. [ASAP/ALAP/Left_Edge Algorithms] Σ i=1…n #instances i * Latency i –Area Σ i=1…n #instances i * Area i –Power Σ i=1…n #instances i * Power i RC delays are not considered in this and assuming to be minimal and impact to the overall CF is less.

18. © Ramakrishna18 Conclusions Strategies for optimizing has to be user driven through some constraints Power poses a unique challenge in terms of the design realization. Design partitioning can improve the overall cost in terms of latency, area & power.