1. Technion – Israel Institute of Technology Faculty of Electrical Engineering NOC Seminar Error Handling in Wormhole Networks Author: Amit Berman Mentor: Prof. Idit Keidar April, 2008

2. Introduction – “A flit with a bad day” [8] Module Crosstalk Glitch from Aggressive Voltage Scaling Radiation EMI Process Variations ‘ 11100 ’‘ 11000 ’ Radiation Alpha particles or cosmic radiation in high integration Process Variations Parameters Uncertainty ‘ 10000 ’ ‘ 00000 ’ ‘ 11110 ’‘ 11100 ’ Signal Glitch Aggressive voltage scaling 0.7Vcc Crosstalk noise Coupling capacitance between wires ‘11111’ ‘11110’ ‘ 11000 ’‘ 10000 ’ Electro-Magnetic Interference (EMI) High frequency, long interconnects

3.  “Conventional” Circuit Design Techniques Spacing Shielding Repeaters  Future Research : Handling errors moves form physical layer to data-link layer Error detection/correction Codes Router Encoder Decoder Router Decoder Encoder NoC Interconnects Error Protection Techniques

4. Analysis of Error Recovery Schemes for NoC Murali et al. ‘05  Error Protection Flow Control Switch-to-Switch (a) End-to-End (b)  Error Protection Codes: Error Detection Codes Error Correction Codes Hybrid schemes Each coding scheme fits different reliability demands

5. Fault Model Notation and Error Control Scheme for Switch to Switch Buses on NoC Zimmer et al. ‘03  Fault Model Notation  Interleaving vs. Error Protection Investigation

6. Clear borders for coding according to reliability spec Fault Model Notation and Error Control Scheme for Switch to Switch Buses on NoC Zimmer et al. ‘03 MB-maximum bandwidth GI-Guaranteed Integrity ML-Maximum latency HR-High Reliability

7. Micro Modem Mogenshtein et al. ‘04  Network interface element  Implements several concepts of wireless RF digital communication Implementation complexity needs to be considered

8. Exploring Fault-Tolerant NoC Architectures Park et al. ‘06  flit-based HBH retransmission scheme  In addition error protection will handle deadlock state Implementation for high reliability requirements

9. Low Power and Error Coding for NoC Traffic Vitkovski et al. ‘04  Compares efficiency of low power coding for error reduction vs. error control coding Error Control Coding Achieves better results then Low Power Coding

10. New Proposal: Embedded Error Protection Method utilizing Packets Data-Dependent Routing Mechanism '0101''0111'  Common error protection techniques use known codes  Efficient coding approach would be application-specific code  Embedded error protection coding is proposed, where the routing is determine upon data manipulation

11. Parity is 1 – suppose to be Y-X, error detected  X-Y/Y-X Example  Parity based Packet Header Error Protection Y-X Path (Routers Include Parity Check) '0101' Parity is 0 = X-Y routing '0111' New Proposal: Embedded Error Protection Method utilizing Packets Data-Dependent Routing Mechanism

12.  Future Research:  Application to various routing techniques e.g. source routing  Cost function considerations  Power and Error Protection Efficiency comparing other Coding techniques New Proposal: Embedded Error Protection Method utilizing Packets Data-Dependent Routing Mechanism Minimum Overhead, Balanced, Scalable Method

13. References [1] H. Zimmer, A. Jantsch, "Fault Model Notation and Error Control Scheme for Switch to Switch buses on NoC".CODES ISSS 2003, pp. 188-193. [2] S. Murali, T. Theocharides, N. Vijaykrishnan, M.J Irwin, L. Benini, G. Micheli, "Analysis of Error Recovery Schemes for Networks on Chips", IEEE Design&Test of Computers 2005, pp. 434-442. [3] A. Mogenshtein, E. Bolotim, I. Cidon, A. Kolodny, R. Ginosar, "Micro Modem – Reliability Solution For NoC Communications", ICECS 2004, pp. 483-486. [4] D. Park, C. Nicopoulos, J. Kim, N. Vijaykrishnan, C.R. Das, "Exploring Fault-Tolerant NoC Architectures", IEEE DSN 2006, pp. 93-104. [5] A. Vitkovski, R. Haukilahti, A. Jantsch, E. Nilsson, "Low Power and Error Coding for Network-on-Chip Traffic", Norchip Conference Proc., 2004. pp. 20-23. [6] G. Micheli, L. Benini, "Networks on Chips – Technology and Tools", Morgan Kaufmann Publishers 2006, pp. 75-139. [7] P. Vellanki, N. Banerjee, K.S. Chatha, "Quality-of-Service and Error Control Techniques for Mesh-Based Network-on-Chip Architectures", Integration 2005, pp. 353-382. [8] J. Nurmi, H. Tenhunen, J. Isoaho, A. Jantsch, "Interconnect-Centric Design for Advanced SOC and NOC", Kluwer Academic Publishers 2004, pp. 155-170. [9] R. Gindin, I. Cidon, I. Keidar, "NoC-Based FPGA: Architecture and Routing", NOCS 2007, pp.253-264. [10] M. Mutyam, "Selective shielding: A Crosstalk-Free Bus Encoding Technique", IEEE ICCAD 2007, pp.618-621. [11] International Technology Roadmap for Semiconductors, 2001.

14. The End Questions? Thanks for your attention