1. ECE2030 Introduction to Computer Engineering Lecture 11: Building Blocks for Combinational Logic (2) Decoders/Encoders, Comparators Prof. Hsien-Hsin Sean Lee School of Electrical and Computer Engineering Georgia Tech

2. 2 1-to-2-Line DecoderAD1D0 001 110 D0 D1 A

3. 3 N-to-M-Line Decoder (2 N  M) A1A0D3D2D1D0 000001 010010 100100 111000 D0D0 D1D1 D2D2 D3D3 2-to-4-linedecoder A0A0 A1A1

4. 4 2-to-4-Line Decoder A1A0D3D2D1D0 000001 010010 100100 111000 How about if no one should be enabled ? A1 A0 D0 D1 D2 D3

5. 5 2-to-4-Line Decoder w/ Enable EnA1A0D3D3 D2D2 D1D1 D0D0 0XX0000 1000001 1010010 1100100 1111000 D0D0 D1D1 D2D2 D3D3 2-to-4-linedecoder A0A0 A1A1 En

6. 6 2-to-4-Line Decoder w/ Enable EnA1A0D3D3 D2D2 D1D1 D0D0 0XX0000 1000001 1010010 1100100 1111000 A1 A0 D0 D1 D2 D3 En

7. 7 3-to-8-Line Decoder A2A1A0D7D7 D6D6 D5D5 D4D4 D3D3 D2D2 D1D1 D0D0 00000000001 00100000010 01000000100 01100001000 10000010000 10100100000 11001000000 11110000000 Truth Table

8. 8 3-to-8-Line Decoder A2A1A0D7D7 D6D6 D5D5 D4D4 D3D3 D2D2 D1D1 D0D0 00000000001 00100000010 01000000100 01100001000 10000010000 10100100000 11001000000 11110000000 Truth Table

9. 9 3-to-8-Line Decoder A2A1A0D7D6D5D4D3D2D1D0 00000000001 00100000010 01000000100 01100001000 10000010000 10100100000 11001000000 11110000000 D0D0 D1D1 D2D2 D3D3 2-to-4-linedecoder A0A0 A1A1 En D0D0 D1D1 D2D2 D3D3 D0D0 D1D1 D2D2 D3D3 2-to-4-linedecoder A0A0 A1A1 D4D4 D5D5 D6D6 D7D7 A0A0 A1A1 A2A2

10. 10 Implementing Logic w/ Decoder D0D0 D1D1 D2D2 D3D3 3-to-8-linedecoder A0A0 A1A1 A2A2 D4D4 D5D5 D6D6 D7D7 X Y Z F1 F2

11. 11 BCD-to-7- Segment Decoder BCD-to-7-Segment Decoder Another kind of decoder a b c d e f g a b c d e f g A B C D

12. 12 BCD-to-7- Segment Decoder BCD-to-7-Segment Decoder Another kind of decoder a b c d e f g a b c d e f g A B C D a b c d e g f

13. 13 BCD-to-7- Segment Decoder BCD-to-7-Segment Decoder Decode “2” and show a b c d e f g a b c d e f g A B C D a b c d e g f 0 0 1 0 1 1 0 1 1 1 0

14. 14 BCD-to-7- Segment Decoder BCD-to-7-Segment Decoder Decode “4” and show a b c d e f g a b c d e f g A B C D a b c d e g f 0 1 0 0 0 1 1 0 0 1 1

15. 15 BCD-to-7-Seg. Decoder Truth Table ABCDabcdefg 000001111110 100010110000 200101101101 300111111001 401000110011 501011011011 601100011111 701111110000 810001111111 910011110011 >10All other inputs0000000

16. 16 Design Each Output Individually  “a” ABCDa 000001 100010 200101 300111 401000 501011 601100 701111 810001 910011 >10All other inputs0 00011110 00 1011 01 0110 11 0000 10 1100 AB CD

17. 17 Design Each Output Individually  “b” ABCDb 000001 100011 200101 300111 401001 501010 601100 701111 810001 910011 >10All other inputs0 00011110 00 1111 01 1010 11 0000 10 1100 AB CD

18. 18 M-to-N-Line Encoder (M  2 N ) D0D0 D1D1 D2D2 D3D3 2-to-4-lineDecoder A0A0 A1A1 En D0D0 D1D1 D2D2 D3D3 4-to-2-lineEncoder A0A0 A1A1 Ac

19. 19 4-to-2 Encoder D3D2D1D0A1A0 000100 001001 010010 100011 Since Dx=1 only in one column at a time A0 = D1 + D3 A1 = D2 + D3 00011110 00 X0X1 01 0XXX 11 XXXX 10 1XXX D3 D2 D1 D0 For A0 00011110 00 X0X0 01 1XXX 11 XXXX 10 1XXX D3 D2 D1 D0 For A1

20. 20 8-to-3 Encoder D7D6D5D4D3D2D1D0A2A1A0 00000001000 00000010001 00000100010 00001000011 00010000100 00100000101 01000000110 10000000111 Since Dx=1 only in one column at a time A0 = D1 + D3 + D5 + D7 A1 = D2 + D3 + D6 + D7 A2 = D4 + D5 + D6 + D7

21. 21 Example 1 of an Encoder Only point to one single reading at a time.

22. 22 Example 2 of an Encoder D0D0 D1D1 D2D2 D3D3 8-to-3-lineEncoder A0A0 A1A1 A2A2 D4D4 D5D5 D6D6 D7D7 Amy Brian Cathy Dave Ellen Frank Gina Hugh Ac 0 0 0 0 Active or not 1 1 0 1 ? ? ? 1

23. 23 8-to-3 Priority Encoder D7D6D5D4D3D2D1D0A2A1A0Active 000000000000 000000010001 0000001X0011 000001XX0101 00001XXX0111 0001XXXX1001 001XXXXX1011 01XXXXXX1101 1XXXXXXX1111

24. 24 4-to-2 Priority Encoder D3D2D1D0A1A0Active 0000000 0001001 001X011 01XX101 1XXX111 00011110 00 0000 01 1111 11 1111 10 1111 D3 D2 D1 D0 For A1 Or using simplification property

25. 25 4-to-2 Priority Encoder D3D2D1D0A1A0Active 0000000 0001001 001X011 01XX101 1XXX111 00011110 00 0011 01 0000 11 1111 10 1111 D3 D2 D1 D0 For A0 Or using simplification property

26. 26 4-to-2 Priority Encoder D3D2D1D0A1A0Active 0000000 0001001 001X011 01XX101 1XXX111 00011110 00 0111 01 1111 11 1111 10 1111 D3 D2 D1 D0 For Active

27. 27 4-to-2 Priority Encoder Schematic D3 D2 D1 D0 A1 A0 Active

28. 28 8-to-3 Priority Encoder (A2) D7D6D5D4D3D2D1D0A2A1A0Active 000000000000 000000010001 0000001X0011 000001XX0101 00001XXX0111 0001XXXX1001 001XXXXX1011 01XXXXXX1101 1XXXXXXX1111

29. 29 8-to-3 Priority Encoder (A1) D7D6D5D4D3D2D1D0A2A1A0Active 000000000000 000000010001 0000001X0011 000001XX0101 00001XXX0111 0001XXXX1001 001XXXXX1011 01XXXXXX1101 1XXXXXXX1111

30. 30 8-to-3 Priority Encoder (A0) D7D6D5D4D3D2D1D0A2A1A0Active 000000000000 000000010001 0000001X0011 000001XX0101 00001XXX0111 0001XXXX1001 001XXXXX1011 01XXXXXX1101 1XXXXXXX1111

31. 31 8-to-3 Priority Encoder (All) D7D6D5D4D3D2D1D0A2A1A0Active 000000000000 000000010001 0000001X0011 000001XX0101 00001XXX0111 0001XXXX1001 001XXXXX1011 01XXXXXX1101 1XXXXXXX1111

32. 32 1-bit Magnitude Comparator ABA?B 00A=B 01A<B 10A>B 11A=B AB A > B A = B A < B Single bit comparison

33. 33 2-bit Magnitude Comparator (unsigned) AB A > B A = B A < B Two-bit comparison 2 2 A1A0B1B0A1A0B1B0

34. 34 2-bit Magnitude Comparator (unsigned) AB A > B A = B A < B Two-bit comparison 2 2 A1A0B1B0A1A0B1B0

35. 35 3-bit Magnitude Comparator (unsigned) Three-bit comparison A2A1A0B2B1B0A2A1A0B2B1B0 AB A > B A = B A < B 3 3

36. 36 4-bit Magnitude Comparator (unsigned) Four-bit comparison A3A2A1A0B3B2B1B0A3A2A1A0B3B2B1B0 AB A > B A = B A < B 4 4

37. 37 4-bit Magnitude Comparator B3A3A2A1A0B2B1B0 X3 X2 X1 X0 A>BA<B A=B

38. 38 Cascading Comparator AB A > B A = B A < B 4 4 AGTBin AGTBout AEQBout ALTBout Inputs from Prior stage Lower order bits (Lower order bits) AEQBin ALTBin Extra Comb. Logic Outputs to Next stage Higher order bits (Higher order bits) AGTBout = (A>B) + (A=B) · AGTBin AEQBout = (A=B) · AEQBin ALTBout = (A<B) + (A=B) · ALTBin

39. 39 16-bit Cascading Comparator AB AGTBin AEQBin ALTBin 4 4 AGTBout AEQBout ALTBout A[3:0] B[3:0] AB AGTBin AEQBin ALTBin 4 4 AGTBout AEQBout ALTBout A[7:4] B[7:4] AB AGTBin AEQBin ALTBin 4 4 AGTBout AEQBout ALTBout A[11:8] B[11:8] AB AGTBin AEQBin ALTBin 4 4 AGTBout AEQBout ALTBout A[15:12] B[15:12] 0 1 0 A>B A<B A=B B[15:0] A[15:0]