1. PROCESSOR PIPELINING YASSER MOHAMMAD

2. SINGLE DATAPATH DESIGN

3. ELEMENT USAGE DURING EXECUTION

4. ENTER STAGE REGISTERS

5. SEQUENCE OF OPERATION OF A LW INSTRUCTION

10. CORRECTED WB IN LW

11. LW

12. THIRD STAGE OF SW

15. KEY POINTS  Each component can be used in at most one stage to avoid structural hazards  Data needed in later stages can be passed through stage registered from the generating stage  Always check where current addresses are coming from

16. DRAWING PIPELINES

18. DESIGNING A CONTROLLER FOR THE PIPELINE  Take as much as you can from the single clock cycle design  See the world using rose-colored glasses  Steps:  Label the lines  Divide control lines per stage (remember one component one stage)  Design a control circuit for each

19. THE LINES

20. ALU CONTROL

22. CONTROL LINES

23. CONTROL SIGNAL PASSING

24. THE COMPLETE BEAST

25. HAZARDS  sub $2, $1,$3  and $12,$2,$5  or $13,$6,$2  add $14,$2,$2  sw $15,100($2)

26. IN THE PIPELINE 1a. EX/MEM.RegisterRd = ID/EX.RegisterRs 1b. EX/MEM.RegisterRd = ID/EX.RegisterRt 2a. MEM/WB.RegisterRd = ID/EX.RegisterRs 2b. MEM/WB.RegisterRd = ID/EX.RegisterRt

27. FORWARDING HARDWARE  Ignores forwarding to a store

29. LOOK CAREFULLY. ANY HAZARDS?

30. THE DATAPATH WITH FORWARDING AND ITS CONTROL

31. Lw $s0, 0($s1) Sw $s0,4($s1)

32. DEALING WITH THE IMMEDIATE

33. WHEN STALLING IS A MUST …. How many stalls will we need: Without forwarding? With Forwarding?

34. NOTES ON STALLING  When stalling in ID, we must stall in IF. Why?  How? Freeze PC and IF/ID

35. SRALLING + FORWARDING HARDWARE

36. CONTROL HAZARDS

37. RESOLUTION 1: PREDICT BRANCH TAKEN  Continue fetching  If the branch is taken (known in the MEM stage of the branch)  Set all control signals in IF/ID, ID/EX,EX/MEM to unasserted (0)  DONE

38. RESOLUTION 2: DECIDE EARLIER  Most branches use simple tests that do not require a complete ALU  What do we need?  Calculate the address of the branch early  Add an ADDER in the ID stage  Compute the decision to branch early  More involved but can be done in ID(for equality at least)  Another source of data hazards. What is it?  New logic is needed to forward to ID from EX/MEM or MEM/WB  Extra sources of stalling:  R-instruction followed by branch  Load followed by branch Forwarding TO the barnch in ID One stall Two stalls

39. DYNAMIC BRANCH PREDICTION  Branch prediction buffer  Branch history table  Indexed by LSBs of the branch address  Prediction helps in decision calculation but not address calculation  Use Delayed branch  Branch target buffer  Global branch behavior  Tournament predictors

40. DELAYED BRANCH  Only effective for short pipelines  The compiler/assembler is responsible of rescheduling.

41. PUTTING IT ALL TOGETHER

42. EXCEPTIONS AND INTERRUPTS  Arithmetic overflow  Undefined instruction  Basic action  Save PC to EPC and Cause to Cause  call the OS (by jumping to 0x 8000 0180)  How does the OS know the reason of the exception:  Cause register (MIPS)  Vectored interrupts (x86)

43. PIPELINED IMPLEMENTATION  Exceptions are control hazards