1. Machine Structures Lecture 19 – CPU Design: Designing a Single-cycle CPU, pt 2 Halloween plans?  Try the Castro, SF! halloweeninthecastro.com Tomorrow 2005-10-31, runs until 11pm …go at least once… Happy Halloween, everyone!

2. How to Design a Processor: step-by-step 1. Analyze instruction set architecture (ISA) => datapath requirements meaning of each instruction is given by the register transfers datapath must include storage element for ISA registers datapath must support each register transfer 2. Select set of datapath components and establish clocking methodology 3. Assemble datapath meeting requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic

3. Step 3: Assemble DataPath meeting requirements Register Transfer Requirements  Datapath Assembly Instruction Fetch Read Operands and Execute Operation

4. 3a: Overview of the Instruction Fetch Unit The common RTL operations Fetch the Instruction: mem[PC] Update the program counter:  Sequential Code: PC  PC + 4  Branch and Jump: PC  “something else” 32 Instruction Word Address Instruction Memory PC clk Next Address Logic

5. 3b: Add & Subtract R[rd] = R[rs] op R[rt] Ex.: addU rd,rs,rt Ra, Rb, and Rw come from instruction’s Rs, Rt, and Rd fields ALUctr and RegWr: control logic after decoding the instruction 32 Result ALUctr clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers RsRtRd ALU oprsrtrdshamtfunct 061116212631 6 bits 5 bits Already defined the register file & ALU

6. Clocking Methodology 存储单元由同样的边缘定时 物理设备, flip-flops (FF) 和组合逻辑会有一些延时 门电路 : 输入引起输出变化之间有延时 在 FF D 输入端的信号必须稳定，然后，激发时钟边缘才允许信 号 FF (set-up time) 中通过, 因此这里也会有 clock-to-Q 延时 “ 关键路径 Critical path” ( 通过逻辑电路的最长路径 ) 确定时钟周期的长度 Clk........................

7. Register-Register Timing: One complete cycle Clk PC Rs, Rt, Rd, Op, Func ALUctr Instruction Memory Access Time Old ValueNew Value RegWrOld ValueNew Value Delay through Control Logic busA, B Register File Access Time Old ValueNew Value busW ALU Delay Old ValueNew Value Old ValueNew Value Old Value Register Write Occurs Here 32 ALUctr clk busW RegWr 32 busA 32 busB 55 RwRaRb RegFile RsRt ALU 5 Rd

8. 3c: Logical Operations with Immediate R[rt] = R[rs] op ZeroExt[imm16] ] oprsrtimmediate 016212631 6 bits16 bits5 bits immediate 0161531 16 bits 0 0 0 0 0 0 0 0 32 ALUctr clk busW RegWr 32 busA 32 busB 55 RwRaRb RegFile RsRt ALU 5 Rd

9. 3c: Logical Operations with Immediate R[rt] = R[rs] op ZeroExt[imm16] ] oprsrtimmediate 016212631 6 bits16 bits5 bits immediate 0161531 16 bits 0 0 0 0 0 0 0 0 Already defined 32-bit MUX; Zero Ext? What about Rt register read?? 32 ALUctr clk RegWr 32 busA 32 busB 55 RwRaRb RegFile Rs Rt Rd ZeroExt 3216 imm16 ALUSrc 01 0 1 ALU 5 RegDst

10. 3d: Load Operations R[rt] = Mem[R[rs] + SignExt[imm16]] Example: lw rt,rs,imm16 oprsrtimmediate 016212631 6 bits16 bits5 bits 32 ALUctr clk RegWr 32 busA 32 busB 55 RwRaRb RegFile Rs Rt Rd ZeroExt 3216 imm16 ALUSrc 01 0 1 ALU 5 RegDst

11. 3d: Load Operations R[rt] = Mem[R[rs] + SignExt[imm16]] Example: lw rt,rs,imm16 oprsrtimmediate 016212631 6 bits16 bits5 bits 32 ALUctr clk busW RegWr 32 busA 32 busB 55 RwRaRb RegFile Rs Rt Rd RegDst Extender 3216 imm16 ALUSrc ExtOp MemtoReg clk Data In 32 MemWr 01 0 1 ALU 0 1 WrEnAdr Data Memory 5 ?

12. 3e: Store Operations Mem[ R[rs] + SignExt[imm16] ] = R[rt] Ex.: sw rt, rs, imm16 oprsrtimmediate 016212631 6 bits16 bits5 bits 32 ALUctr clk busW RegWr 32 busA 32 busB 55 RwRaRb RegFile Rs Rt Rd RegDst Extender 3216 imm16 ALUSrc ExtOp MemtoReg clk Data In 32 MemWr 01 0 1 ALU 0 1 WrEnAdr Data Memory 5

13. 3e: Store Operations Mem[ R[rs] + SignExt[imm16] ] = R[rt] Ex.: sw rt, rs, imm16 oprsrtimmediate 016212631 6 bits16 bits5 bits 32 ALUctr clk busW RegWr 32 busA 32 busB 55 RwRaRb RegFile Rs Rt Rd RegDst Extender 3216 imm16 ALUSrc ExtOp MemtoReg clk Data In 32 MemWr 01 0 1 ALU 0 1 WrEnAdr Data Memory 5

14. 3f: The Branch Instruction beq rs, rt, imm16 mem[PC] Fetch the instruction from memory Equal = R[rs] == R[rt] Calculate branch condition if (Equal) Calculate the next instruction’s address  PC = PC + 4 + ( SignExt(imm16) x 4 ) else  PC = PC + 4 oprsrtimmediate 016212631 6 bits16 bits5 bits

15. Datapath for Branch Operations beq rs, rt, imm16 Datapath generates condition (equal) oprsrtimmediate 016212631 6 bits16 bits5 bits Already have mux, adder, need special sign extender for PC, need equal compare (sub?) imm16 clk PC 00 4 nPC_sel PC Ext Adder Mux Inst Address 32 ALUctr clk busW RegWr 32 busA 32 busB 55 RwRaRb RegFile RsRt ALU 5 = Equal

16. Putting it All Together:A Single Cycle Datapath imm16 32 ALUctr clk busW RegWr 32 busA 32 busB 55 RwRaRb RegFile Rs Rt Rd RegDst Extender 3216 imm16 ALUSrcExtOp MemtoReg clk Data In 32 MemWr Equal Instruction Imm16RdRtRs clk PC 00 4 nPC_sel PC Ext Adr Inst Memory Adder Mux 01 0 1 = ALU 0 1 WrEnAdr Data Memory 5

17. An Abstract View of the Implementation Data Out clk 5 RwRaRb Register File Rd Data In Data Addr Ideal Data Memory Instruction Address Ideal Instruction Memory PC 5 Rs 5 Rt 32 A B Next Address Control Datapath Control Signals Conditions clk ALU

18. Peer Instruction A. Our ALU is a synchronous device B. We should use the main ALU to compute PC=PC+4 C. The ALU is inactive for memory reads or writes. ABC 1: FFF 2: FFT 3: FTF 4: FTT 5: TFF 6: TFT 7: TTF 8: TTT

19. °5 steps to design a processor 1. Analyze instruction set => datapath requirements 2. Select set of datapath components & establish clock methodology 3. Assemble datapath meeting the requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic °Next time! Summary: Single cycle datapath Control Datapath Memory Processor Input Output