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EE141 Combinational Circuits 1 Chapter 6 (I) Designing Combinational Logic Circuits Dynamic CMOS LogicDynamic CMOS Logic V1.0 5/4/2003
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EE141 Combinational Circuits 2 Revision Chronicle 5/4: Split Chapter 6 into two parts: Part I focuses on Static and Pass Transistor Logic. Part II focuses on Dynamic Logic
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EE141 Combinational Circuits 3 Dynamic CMOS In static circuits at every point in time (except when switching), the output is connected to either GND or V DD via a low resistance path. Fan-in of n requires 2n (n N-type + n P-type) devices Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes. Requires on n + 2 (n+1 N-type + 1 P-type) transistors
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EE141 Combinational Circuits 4 Dynamic Gate In 1 In 2 PDN In 3 MeMe MpMp Clk Out CLCL Clk A B C MpMp MeMe Two phase operation Precharge (CLK = 0) Evaluate (CLK = 1)
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EE141 Combinational Circuits 5 Dynamic Gate In 1 In 2 PDN In 3 MeMe MpMp Clk Out CLCL Clk A B C MpMp MeMe Two phase operation Precharge (Clk = 0) Evaluate (Clk = 1) on off 1 on ((AB)+C)
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EE141 Combinational Circuits 6 Conditions on Output Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation. Inputs to the gate can make at most one transition during evaluation. Output can be in the high impedance state during and after evaluation (PDN off), state is stored on C L
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EE141 Combinational Circuits 7 Properties of Dynamic Gates Logic function is implemented by the PDN only number of transistors is N + 2 (versus 2N for static complementary CMOS) Full swing outputs (V OL = GND and V OH = V DD ) Non-ratioed - sizing of the devices does not affect the logic levels Faster switching speeds reduced load capacitance due to lower input capacitance (C in ) reduced load capacitance due to smaller output loading (Cout) no I sc, so all the current provided by PDN goes into discharging C L
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EE141 Combinational Circuits 8 Properties of Dynamic Gates Overall power dissipation usually higher than static CMOS no static current path ever exists between V DD and GND (including P sc ) no glitching Higher transition probabilities Extra load on Clk PDN starts to work as soon as the input signals exceed V Tn, so V M, V IH and V IL equal to V Tn Low noise margin (NM L ) Needs a precharge/evaluate clock
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EE141 Combinational Circuits 9 Issues in Dynamic Design 1: Charge Leakage CLCL Clk Out A MpMp MeMe Leakage sources CLK V Out Precharge Evaluate Dominant component is subthreshold current
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EE141 Combinational Circuits 10 Solution to Charge Leakage CLCL Clk MeMe MpMp A B Out M kp Same approach as level restorer for pass-transistor logic Keeper
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EE141 Combinational Circuits 11 Issues in Dynamic Design 2: Charge Sharing CLCL Clk CACA CBCB B=0 A Out MpMp MeMe Charge stored originally on C L is redistributed (shared) over C L and C A leading to reduced robustness
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EE141 Combinational Circuits 12 Charge Sharing Example C L =50fF Clk AA B B B!B!B CC Out C a =15fFC c =15fFC b =15fFC d =10fF
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EE141 Combinational Circuits 13 Charge Sharing B 0 Clk X C L C a C b A Out M p M a V DD M b Clk M e
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EE141 Combinational Circuits 14 Solution to Charge Redistribution Clk MeMe MpMp A B Out M kp Clk Precharge internal nodes using a clock-driven transistor (at the cost of increased area and power)
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EE141 Combinational Circuits 15 Issues in Dynamic Design 3: Backgate Coupling C L1 Clk B=0 A=0 Out1 MpMp MeMe Out2 C L2 In Dynamic NANDStatic NAND =1 =0
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EE141 Combinational Circuits 16 Backgate Coupling Effect Voltage Time, ns Clk In Out1 Out2
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EE141 Combinational Circuits 17 Issues in Dynamic Design 4: Clock Feedthrough CLCL Clk B A Out MpMp MeMe Coupling between Out and Clk input of the precharge device due to the gate to drain capacitance. The voltage of Out can rise above V DD. The fast rising (and falling edges) of the clock couple to Out.
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EE141 Combinational Circuits 18 Clock Feedthrough Clk In 1 In 2 In 3 In 4 Out In & Clk Out Time, ns Voltage Clock feedthrough
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EE141 Combinational Circuits 19 Other Effects Capacitive coupling Substrate coupling Minority charge injection Supply noise (ground bounce)
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EE141 Combinational Circuits 20 Cascading Dynamic Gates Clk Out1 In MpMp MeMe MpMp MeMe Clk Out2 V t ClkIn Out1 Out2 VV V Tn Only 0 1 transitions allowed at inputs!
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EE141 Combinational Circuits 21 Domino Logic In 1 In 2 PDN In 3 MeMe MpMp Clk Out1 In 4 PDN In 5 MeMe MpMp Clk Out2 M kp 1 1 1 0 0 0 0 1
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EE141 Combinational Circuits 22 Why Domino? Clk In i PDN In j In i In j PDN In i PDN In j In i PDN In j Like falling dominos!
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EE141 Combinational Circuits 23 Properties of Domino Logic Only non-inverting logic can be implemented Very high speed static inverter can be skewed, only L-H transition Input capacitance reduced – smaller logical effort
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EE141 Combinational Circuits 24 Designing with Domino Logic M p M e V DD PDN Clk In 1 2 3 Out1 Clk M p M e V DD PDN Clk In 4 Clk Out2 M r V DD Inputs = 0 during precharge Can be eliminated!
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EE141 Combinational Circuits 25 Footless Domino The first gate in the chain needs a foot switch Precharge is rippling – short-circuit current A solution is to delay the clock for each stage
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EE141 Combinational Circuits 26 Differential (Dual Rail) Domino A B MeMe MpMp Clk Out = AB !A!A!B!B M kp Clk Out = AB M kp MpMp Solves the problem of non-inverting logic 1 0 on off
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EE141 Combinational Circuits 27 np-CMOS In 1 In 2 PDN In 3 MeMe MpMp Clk Out1 In 4 PUN In 5 MeMe MpMp Clk Out2 (to PDN) 1 1 1 0 0 0 0 1 Only 0 1 transitions allowed at inputs of PDN Only 1 0 transitions allowed at inputs of PUN
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EE141 Combinational Circuits 28 NORA Logic In 1 In 2 PDN In 3 MeMe MpMp Clk Out1 In 4 PUN In 5 MeMe MpMp Clk Out2 (to PDN) 1 1 1 0 0 0 0 1 to other PDN’s to other PUN’s WARNING: Very Sensitive to Noise!
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