1. 3-phase half-wave converter

3. 1.The mean output voltage is zero for 2.Negative average output voltage occurs when 3.Power inversion is possible, if a load with an e.m.f. to assist the current flow. In general, for an m-phase half-wave converter, the mean output voltage is given by If m = 3 (3-phase),

4. With an RL load, at V dc = 0, the load current falls to zero. Thus, continuous load current does not flow for an RL load for α ≥∏/2.

5. Half-wave controlled rectifier with free-wheeling diode

6. The diode prevents the load voltage from going negative, thus inversion is not possible For α≤∏/6, without voltage zeros occurring, the mean output voltage is given by For α ≥∏/6, voltage zeros occur and the negative portions in the waveforms do not occur. The mean output voltage is given by A delay angle of greater than would imply a negative output voltage, clearly not possible with a free- wheeling load diode.

7. 3-phase full converter

9. For, the output voltage is non-zero at all instances, hence the load current is continuous for any passive load. Beyond, the load current may be discontinuous. For, the current is always discontinuous for passive loads. Power inversion is possible with an e.m.f. source. If inversion is not required, a free-wheeling diode is normally used

11. Overlap Overlap is the phenomenon due to the effect of source inductance on the a.c. side. The current commutation is delayed due to the source inductance which is normally the leakage reactance of a transformer (as X >> R for a transformer, the source resistance is usually neglected).

12. The waveforms with commutation period, denoted by  during which both the outgoing diode and incoming diode are conducting. This period is also known as “overlap” period. During the overlap period, the load current is the addition of the two diode currents, the assumption being made that the load is inductive enough to give a constant load current. The load voltage is the mean of the two conducting phases during overlap period. The effect of overlap is to reduce the mean output voltage.

14. A circulating current i can be considered to flow in the closed path formed by the 2 conducting diodes D 1 and D 2. Ignoring the diode voltage drop The voltage V 2 - V 1 = the difference between the two phases = 0 at time zero. (t = 0) For t > 0, the voltage V m : peak value of the phase voltage V L :r.m.s. line voltage Therefore,

15. At t = 0, i = 0 Hence, Proof of v 2 - v 1,

16. If the datum is shifted by 150 0,

17. The overlap is complete when i = I L, at The mean output voltage is given by or V dc = V dc without overlap - reduction of V dc due to overlap.

18. (i) V dc without overlap = (ii) Reduction of Vdc due to overlap

20. Overlap in controlled 3-phase converter It can be seen that with a firing delay angle , a finite voltage is present, where t = time from the start of commutation, when i = 0. which gives Overlap being complete when i = I L and  t = .

21. Compared to the uncontrolled case  = 0 0, the overlap angle  is shorter and the current change during commutation will be towards a linear variation. The mean voltage of the load is given by : - Remark : 1.The location of the waveform during overlap is at a position midway between the outgoing and incoming voltages. 2.For the 2-phase waveform, the load voltage = 0 during overlap period.

22. Overlap for inversion A d.c. machine as the load element, acting as a motor which the converter rectifying. However, if the load voltage V L reverses and the d.c. machine will act as a generator. If the machine runs in the same direction of rotation, it can only generate by having its armature or field connections reversed It is only possible to commutate current from thyristor T 1 to thyristor T 2 while the instantaneous voltage of phase 2 is higher than phase 1 (i.e. while V 2 is less negative than V 1 ). At  = 180 0, V 1 and V 2 and the relative voltage between the two phase after this reverses, making commutation impossible, hence is the limit of operation.

23. When in the inverting mode, it is more usual to designate the firing position as firing advance angle The effect of the overlap period is to delay the commutation. The waveform during overlap has a voltage midway between the incoming and outgoing voltages. If the commutation is not complete before the two commutating phase reach equal voltage values, then transfer of current is impossible as the load current will revert to the outgoing thyristor. The overlap angle  must be less than the firing advance angle . In practice can never be reduced to zero.