1. MSI Combinational logic circuits

2. Outline
Decoders
Multiplexers
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3. Decoders/Demultiplexers
A decoder is a combinational circuit that converts binary information from n inputs to a maximum of unique 2n output lines. If n bit decoded information has unused or don't care combination, the decoder output will have less than 2n outputs.
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4. Decoders/DemultiplexersA D0 D1 1
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5. Decoders/DemultiplexersA B D0 D1 D2 D3 1
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6. Example
Design a 2-input, 4-output combinational logic circuit to decode the 2-bit output of the following function table:
Input
Output X Y A S M D 1
Function
Code
Add 1 00
Sub 01
Mul 10
Div 11
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7. Example Full adder S(A,B,C) = m(1,2,4,7) Cin(A,B,C) = m(1,2,4,7)
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8. Decoder with Enable
A decoder with an enable can function as a demultiplexer. A demultiplexer is a circuit that receives information on a single line and transmits this information on one of possible 2n lines. The selection of a specific output line is controlled by the bit values of n selection lines.
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9. CS Digital Logic
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10. Standard MSI Decoders
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11. Example
Realize Boolean function f = A'B' + AB with a 2:4 decoder
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12. 3:8 Decoder
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13. 4:16 Decoder
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14. Cascading decoders Build a 4:16 decoder using two 74138 decoders.
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15. Encoders
An encoder is a digital circuit that performs the inverse operation of a decoder. An encoder has 2n (or fewer) input lines and n output lines. The output lines generate the binary code corresponding to the input value.
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16. Example
A calculator has four function keys (add, subtract, multiply, divide). Only one of the function keys can be pressed at a time. When a particular key is pressed, that key is encoded according to the following function tab
X = A'S'
Y = A'M'
Function
Code
Add 1 00
Sub 01
Mul 10
Div 11
Input
Output
Line A S M D X Y 1 2 3 4
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17. Example X = A'S' Y = A'M' Input Output Line A S M D X Y 1 2 3 42 3 4
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18. Multiplexers/selectors
Multiplexing means transmitting a large number of information units over a smaller number of channels or lines. A digital multiplexer is a combination circuit that selects binary information from one of many input lines and directs it to a single output line. The selection of a particular input line is controlled by a set of selection lines. Normally, there are 2 input lines and selection lines whose bit combinations determine which input is selected.
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19. 21 Multiplexers s0 z I0 1 I1
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20. 21 Multiplexers Z = s0 I0 + s1 I1 I1 I0 s0 Z 1 CS 3402--Digital Logic1
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21. 41 Multiplexers Z = s1 s0I0 + s1s0 I1 + s1s0 I2 + s1s0 I3 s1 s0 Z I0I0 1 I1 I2 I3
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22. 81 Multiplexers s2 s1 s0 Z I0 1 I1 I2 I3 I4 I5 I6 I7
Z = s2s1s0I0 + s2s1s0 I1 + s2s1s0 I2 + s2s1s0 I3+ s2s1s0I4 + s2s1s0 I5 + s2s1s0 I6 + s2s1s0 I7
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23. Alternative Implementation
The following diagrams show how to construct a 8  1 multiplexer using either 4  1 multiplexers or
2  1 multiplexers.
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24. CS Digital Logic
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25. Example F(A,B,C) = m(0,2,6,7) A B C F 1 CS 3402--Digital Logic1
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26. Example A B C F 1 C'
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27. Examples Implement a 2  1 multiplexer to
F(A,B,C) = m(1,3,5,6)
Implement a 4  1 multiplexer to
F(A,B,C,D) = m(0,1,3,4,8,9.15)
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28. Multiplexer devices There are multiplexers devices in 7400 series,
to-1 multiplexer (24 pins)
to-1 multiplexer (16 pins)
to-1 multiplexer
to-1 multiplexer
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29. Multiplexer devices
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30. Exercises
p , 4.4, 4.5, 4.9, 4.15, 4.16, 4.18, 4.19, 4.20, 4.21, 4.23, 4.25
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