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TMS320C6xx Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004 Architecture C6xx.

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Presentation on theme: "TMS320C6xx Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004 Architecture C6xx."— Presentation transcript:

1 TMS320C6xx Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004 Architecture C6xx

2 2 'C6x - System Block Diagram PERIPHERALSPERIPHERALSPERIPHERALSPERIPHERALS On Chip Ex. Memory Internal Buses Off Chip Ex. Memory Ex. Memory CPU.D1.M1.L1.S1.D2.M2.L2.S2 Regs (B0-B15) Regs (A0-A15) Control Regs Harvard PC

3 3 C6x - Internal Buses VLIW Read Write CPU DMA

4 4 'C6x - System Block Diagram 32/ /64 32 I/O Mappate in memoria Mappate in memoria

5 5 'C6x - Peripherals On Chip Off Chip Each of these peripherals has a module dedicated to them and each of these can exist on the C6x

6 6 EMIF clk1 clk2 clk3 Ad1 Ad2 Ad3 clk0

7 7 Memory Size per device DevicesInternal EMIF A EMIF B C6201,C6701 C6204,C6205 P = 64 kB D = 64 kB 52M Bytes (32-bits wide) N/A C6202 P = 256 kB D = 128 kB C6203 P = 384 kB D = 512 kB C6211 C6711 L1P = 4 kB L1D = 4 kB L2 = 64 kB 128M Bytes (32-bits wide) N/A C M Bytes (16-bits wide) C6713 L1P = 4 kB L1D = 4 kB L2 = 256 kB 128M Bytes (32 - bits wide) N/A C6411 DM642 L1P = 16 kB L1D = 16 kB L2 = 256 kB 128M Bytes (32-bits wide) N/A C6414 C6415 C6416 L1P =16 kB L1D =16 kB L2 = 1 MB 256M Bytes (64-bits wide) 64M Bytes (16-bits wide) HARVARDOff Chip Memory SlowFast

8 8 HPI / XBUS / PCI

9 9 McBSP/ASP and Utopia Bus I 2 C: Protocollo Seriale Sincrono (due linee bidirezionali, clock e dati sincroni, più la massa) ATM: Asynchronous Transfer Mode

10 10 GPIO LED SWITCH

11 11 DMA / EDMA

12 12 Timer / Counter

13 13 Ethernet

14 14 Video Ports

15 15 VCP / TCP - 3G Wireless

16 16 Phase Locked Loop ( PLL )

17 17 Clock Cycle x8

18 18 C6713 Architecture

19 19 C6713-DSK Architecture

20 20 CPLDs

21 21 C6416 Architecture

22 22 C6416-DSK Architecture Slow Fast

23 23 C6x - Family Part Numbering Ex = TMS320 L C PKG A 200 TMS320= TI DSP L = Place holder for voltage levels C6 = C6x family 2 = Fixed/Floating-point core 01 = Memory/peripheral configuration PKG= Pkg designator (actual letters TBD) A = -40 to 85C (blank for 0 to 70C) 200 = Core CPU speed in Mhz

24 24 Architecture Links: Links: C6711 data sheet: tms320c6711.pdf C6711 data sheet: tms320c6711.pdftms320c6711.pdf C6713 data sheet: tms320c6713.pdf C6713 data sheet: tms320c6713.pdftms320c6713.pdf C6416 data sheet: tms320c6416.pdf C6416 data sheet: tms320c6416.pdftms320c6416.pdf User guide C6xx: spru189f.pdf User guide C6xx: spru189f.pdfspru189f.pdf Errata: sprz173c.pdf Errata: sprz173c.pdfsprz173c.pdf


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