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Dirk Stroobandt Ghent University Electronics and Information Systems Department A New Design Methodology Based on System-Level Interconnect Prediction.

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Presentation on theme: "Dirk Stroobandt Ghent University Electronics and Information Systems Department A New Design Methodology Based on System-Level Interconnect Prediction."— Presentation transcript:

1 Dirk Stroobandt Ghent University Electronics and Information Systems Department A New Design Methodology Based on System-Level Interconnect Prediction Talk at SSGRRw2002 January 24th, 2002

2 Dirk Stroobandt, Ghent University 2 Why a priori interconnect prediction? Basic models and Rent’s rule Recent advances in a priori wire length prediction Applications Outline

3 January 24th, 2002Dirk Stroobandt, Ghent University 3 Why a priori interconnect prediction? Basic models and Rent’s rule Recent advances in a priori wire length prediction Applications Outline

4 January 24th, 2002Dirk Stroobandt, Ghent University 4 Interconnect: importance of wires increases (they do not scale as components). A priori: For future designs, very little is known. The sooner information is available, the better. old new Why A Priori Interconnect Prediction?

5 January 24th, 2002Dirk Stroobandt, Ghent University 5 Classical Digital Design Flow X=(ABCD+A+D+A(B+C)) Y=(A(B+C)+AC+D+A(BC+D)) System specification Functional design Logic design Circuit designPhysical designFabricationPackaging and testing

6 January 24th, 2002Dirk Stroobandt, Ghent University 6 Interconnect-centric Design Flow X=(ABCD+A+D+A(B+C)) Y=(A(B+C)+AC+D+A(BC+D)) Packaging and testing Fabrication Circuit design Physical design Logic design Functional design System specification Physical and technological a priori estimations

7 January 24th, 2002Dirk Stroobandt, Ghent University 7 Setting of SLIP Research Domain in the Design Process Circuit design Fabrication Physical design Floorplanning Placement Routing

8 January 24th, 2002Dirk Stroobandt, Ghent University 8 Why a priori interconnect prediction? Basic models and Rent’s rule Recent advances in a priori wire length prediction Applications Outline

9 January 24th, 2002Dirk Stroobandt, Ghent University 9 Components of the Physical Design Step Layout Layout generation CircuitArchitecture

10 January 24th, 2002Dirk Stroobandt, Ghent University 10 Net Terminal / pin The Three Basic Models Circuit model Placement and routing model Model for the architecture Pad Channel Manhattan grid using Manhattan metric Cell Logic block

11 January 24th, 2002Dirk Stroobandt, Ghent University 11 T = t B p Rent’s Rule Normal values: 0.5  p  0.75 Measure for the complexity of the interconnection topology p = Rent exponent Rent’s rule was first described by Landman and Russo* in 1971. For average number of terminals and blocks per module in a partitioned design: t  average # term./block * B. S. Landman and R. L. Russo. “On a pin versus block relationship for partitions of logic graphs.” IEEE Trans. on Comput., C-20, pp. 1469-1479, 1971. (simple) 0  p  1 (complex)

12 January 24th, 2002Dirk Stroobandt, Ghent University 12 Why a priori interconnect prediction? Basic models and Rent’s rule Recent advances in a priori wire length prediction Applications Outline

13 January 24th, 2002Dirk Stroobandt, Ghent University 13 1. Partition the circuit into 4 modules of equal size such that Rent’s rule applies (minimal number of pins). 2. Partition the Manhattan grid in 4 subgrids of equal size in a symmetrical way. Donath’s* Hierarchical Placement Model * W. E. Donath. Placement and Average Interconnection Lengths of Computer Logic. IEEE Trans. on Circuits & Syst., vol. CAS-26, pp. 272-277, 1979.

14 January 24th, 2002Dirk Stroobandt, Ghent University 14 3. Each subcircuit (module) is mapped to a subgrid. 4. Repeat recursively until all logic blocks are assigned to exactly one grid cell in the Manhattan grid. Donath’s Hierarchical Placement Model mapping

15 January 24th, 2002Dirk Stroobandt, Ghent University 15 Donath’s Length Estimation Model Length of the connections at each level? Donath assumes: all connection source and destination cells are uniformly distributed over the grid. Adjacent ( A -) combination Diagonal ( D -) combination

16 January 24th, 2002Dirk Stroobandt, Ghent University 16 Results Donath Scaling of the average length L as a function of the number of logic blocks G : L G 0 5 10 15 20 25 30 11010010 3 10 6 10 5 10 4 10 7 p = 0.7 p = 0.5 p = 0.3 Similar to measurements on placed designs.

17 January 24th, 2002Dirk Stroobandt, Ghent University 17 Results Donath Theoretical average wire length too high by factor of 2 10000 L G 1 2 3 4 6 5 7 101001000 8 experiment theory 0

18 January 24th, 2002Dirk Stroobandt, Ghent University 18 Occupation probability* favours short interconnections (for placement optimization) (darker) Keep wire length scaling by hierarchical placement. Improve on uniform probability for all connections at one level (not a good model for placement optimization). Improving on the Placement Optimization Model * D. Stroobandt and J. Van Campenhout. Accurate Interconnection Length Estimations for Pre- dictions Early in the Design Cycle. VLSI Design, Spec. Iss. on PD in DSM, 10 (1): 1-20, 1999.

19 January 24th, 2002Dirk Stroobandt, Ghent University 19 Occupation Probability: Results 8 Occupation prob. 10000 L G 1 2 3 4 6 5 7 101001000 0 Donath Experiment Use probability on each hierarchical level (local distributions).

20 January 24th, 2002Dirk Stroobandt, Ghent University 20 Effect of the occupation probability on the total distribution: more short wires = less long wires  Average wire length is shorter Occupation Probability: Results

21 January 24th, 2002Dirk Stroobandt, Ghent University 21 Extension to Three-dimensional Grids* * D. Stroobandt and J. Van Campenhout. Estimating Interconnection Lengths in Three- dimensional Computer Systems. IEICE Trans. Inf. & Syst., Spec. Iss. On Synthesis and Verification of Hardware Design, vol. E80-D (no. 10), pp. 1024-1031, 1997. * A. Rahman, A. Fan and R. Reif. System-level Performance Evaluation of Three-dimensional Integrated Circuits. IEEE Trans. on VLSI Systems, Spec. Iss. on SLIP, pp. 671-678, 2000.

22 January 24th, 2002Dirk Stroobandt, Ghent University 22 Anisotropic Systems* * H. Van Marck and J. Van Campenhout. Modeling and Evaluating Optoelectronic Architectures. Optoelectronics II, vol. 2153 of SPIE Proc. Series, pp. 307-314, 1994.

23 January 24th, 2002Dirk Stroobandt, Ghent University 23 Other Extensions Wire length estimates for external nets* Estimates for multi-terminal nets** Global distribution (heterogeneous systems-on-a-chip)*** * D. Stroobandt, H. Van Marck and J. Van Campenhout. Estimating Logic Cell to I/O Pad Lengths in Computer Systems. Proc. SASIMI’97, pp. 192-198, 1997. ** D. Stroobandt. Multi-terminal nets do change conventional wire length distribution models. Proc. Intl. Workshop on System-Level interconnect Prediction, pages 41 – 48, March 2001. *** P. Zarkesh-Ha, J.A. Davis, and J.D. Meindl. Prediction of net length distribution for global interconnections in a heterogeneous system-on-a-chip. IEEE TVLSI, SLIP issue, Dec. 2000.

24 January 24th, 2002Dirk Stroobandt, Ghent University 24 Why a priori interconnect prediction? Basic models and Rent’s rule Recent advances in a priori wire length prediction Applications Outline

25 January 24th, 2002Dirk Stroobandt, Ghent University 25 Extrapolation to future systems: Roadmaps. GTX* et al. Technology Extrapolation * A. Caldwell et al. “GTX: The MARCO GSRC Technology Extrapolation System.” IEEE/ACM DAC, pp. 693-698, 2000 (http://vlsicad.cs.ucla.edu/GSRC/GTX/).

26 January 24th, 2002Dirk Stroobandt, Ghent University 26 Models of achievable routing Required versus available resources limited by routing efficiency, power/ground nets and via impact

27 January 24th, 2002Dirk Stroobandt, Ghent University 27 A Typical Layer Assignment Example Tier type 2 Tier type 1 Tier type 0 Wirelength (mm) Delay (ps) Wire width (  m) 02400224Number of repeaters

28 January 24th, 2002Dirk Stroobandt, Ghent University 28 Optimal Layer Stack Monotonic? 5.4426 7.0002 19.3665 Tier 2 Tier 1 Tier 0 7.1285 20 18 16 14 12 10 8 6 4 2 0 Number of layers per tier type 20 18 16 14 12 10 8 6 4 2 0

29 January 24th, 2002Dirk Stroobandt, Ghent University 29 Three-dimensional Chips Different asymptotic average wire length* * J. Van Campenhout, H. Van Marck, J. Depreitere, J. Dambre, “TITLE” IEEE J. Sel. Topics in Quant. Electr. on Smart Phot. Comp., Interconnects, and Proc. (5)2, 1999, pp. 306 -- 315 Two-dimensional Design size (logic blocks) Three-dimensional p =0.4 p =0.6 p =0.8

30 January 24th, 2002Dirk Stroobandt, Ghent University 30 Three-dimensional Chips Wire length distribution differs significantly* * J. Van Campenhout, H. Van Marck, J. Depreitere, J. Dambre,”TITLE” IEEE J. Sel. Topics in Quant. Electr. on Smart Phot. Comp., Interconnects, and Proc. (5)2, 1999, pp. 306 -- 315 Distribution Rent exponent r Average wire length

31 January 24th, 2002Dirk Stroobandt, Ghent University 31 Effect of Anisotropy Benefits are lower if anisotropy is higher* * J. Van Campenhout, H. Van Marck, J. Depreitere, J. Dambre, “TITLE” IEEE J. Sel. Topics in Quant. Electr. on Smart Phot. Comp., Interconnects, and Proc. (5)2, 1999, pp. 306 -- 315 Number of layers (4096 gates) Average wire length Relative anisotropic cost Average wire length 11 0 4 5 4 3 2 1 51015202528616101214 3 7.5 2.5 6 5 4 3.5 7 6.5 5.5 4.5 Cost = 1 Cost = 16 Cost = 8 Cost = 24

32 January 24th, 2002Dirk Stroobandt, Ghent University 32 What Could It Look Like ? OIIC Project (http://www.elis.rug.ac.be/~jvc/oiic/sysdemo.htm)

33 January 24th, 2002Dirk Stroobandt, Ghent University 33 Conclusion Wire length distribution estimations have evolved a lot in the last few years and have gained accuracy but the work is not finished! Suggested reading (brand new book): D. Stroobandt. A Priori Wire Length Estimates for Digital Design. Kluwer Academic Publishers, 2001. 324 pages, ISBN no. 0 7923 7360 x.

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