1. Statement Of Work Define static processor, DSP Profiles, memory and bus architectures. Define interconnections between DLX and DSP processors while helping Data Path 2 group to develop switching scenarios. Determine bounds and reservation tables and work on applicable optimization issues.

2. SOW (Contd.) Help define decoders for DSP Profiles. Provide needed assistance during system testing.

3. November 3, 2000 Profiles Picked. Static Processor Picked: DLX

4. November 8, 2000 Defined Hardware Profiles. Provided DLX Hardware Details. Provided details for DLX software tools.

5. November 10, 2000 Finalized DSP Hardware Details. Defined overall memory architecture. Current presentation.

6. November 13, 2000 Reservation Tables

7. November 15, 2000 Bounds Preliminary Design Review

8. December 1, 2000 Critical Design Review

9. December 6, 2000 Web-site Final Design Review

10. Plan To Achieve The Goal Create reservation tables for each DSP by 11/13- no risks Determine bounds on each DSP by 11/15 - Dependent on receiving FSFG from Algorithm group.

11. How We Fit In The Big Picture We are designing a hardware architecture optimized to meet the algorithm group’s requirements. The other hardware groups will use the architectural framework we have provided to implement the MPEG2 decoder. We are also providing assistance to the software teams in order to create tools needed for our architecture