1. Time Optimization of HEVC Encoder over X86 Processors using SIMD
Spring 2013 Multimedia Processing EE5359
Advisor: Dr. K. R. Rao
Kushal Shah

2. Objective
With a lot of enhanced coding tools introduced, HEVC is expected to achieve 50% bit rate reductions at similar mean opinion score (MOS) compared with the previous standard H.264/AVC [1].
However, the computational complexity of HEVC has greatly increased, making encoding speed a serious problem in the implementation of HEVC [2].

3. Overview of HEVC [1]
High Efficiency Video Coding (HEVC) is the newest video coding standard of the ITU-T Video Coding Experts Group and the ISO/IEC Moving Picture Experts Group.
The main goal of the HEVC standardization effort is to enable significantly improved compression performance relative to existing standards—in the range of 50% bit-rate reduction for equal perceptual video quality.

4. HEVC Encoder Block Diagram [1]
Fig.1: HEVC encoder block diagram [1]

5. Fig. 2 Macroblocks in HEVC [5]

6. Time Analysis of HEVC Encoder [2][3]
Fig. 3: Time analysis of HEVC encoder [2][3]

7. Time Analysis of HEVC Encoder[2][3]
HEVC utilizes a quadtree structure [4] to support large and flexible block sizes.
The size of a coding unit (CU) can be 64x64, 32x32, 16x16 and 8x8. Each CU is split into one or more prediction units (PU) and transform units (TU).
For PU, the width and height of a PU vary from 4 to 64, indicating that the blocks to be processed in motion compensation (MC) can be as large as 64x64.

8. Time Analysis of HEVC Encoder [2][3]
In motion estimation (ME), sum of absolute differences (SAD) and sum of absolute transformed differences (SATD) of different block sizes are calculated.
Due to the flexible block structure, each 4x4 block will be calculated several times from 4x4 to 64x64 ME, which can be quite time-consuming.

9. 8-Tap and 4-Tap Interpolation[7]
8-Tap Interpolation Filter:
Fig. 4: Interpolation filter for fractional pels in motion compensation [7]

10. Intel SSE Instruction [6]
Streaming SIMD extensions (SSE) are the SIMD instruction set extension over the x86 architecture. It is further enhanced to SSE2, SSE3, SSSE3 and SSE4 subsequently.
SSE contains eight 128-bit registers originally, known as XMM0 through XMM7. The number of registers is extended to sixteen in AMD64.
Each 128-bit register can be divided into two 64-bit integers, four 32-bit integers, eight 16-bit short integers or sixteen 8-bit bytes.
With SSE series instructions, several XMM registers can be operated at the same time, indicating considerable data-level parallelism.

11. Intel SSE Instruction[6]
The PMADDUBSW instruction takes two 128-bit SSE registers as operands, with the first one containing sixteen unsigned 8-bit integers, and the second one containing sixteen signed 8-bit integers. With this instruction, It is only necessary to sum the values in the destination register to get the final results.
Fig 5: SSE Instruction structure [6]

12. Intel SSE Instruction[6]
The PMADDW instruction takes two 64-bit SSE registers as operands, with the first one containing eight unsigned 8-bit integers, and the second one containing eight signed 8-bit integers. This instruction adds and concatenates values of this two operands.
Fig 6: SSE Instruction structure [6]

13. Calculating Motion Vectors[7]
Fig. 7 : Luminance and chrominance row interpolation [7]

14. Fig. 8 Hadamard transform algorithm

15. Fig. 9 Instruction structure for hadamard transform calculation

16. SAD/SSD Calculation [2]
Fig. 10 Instruction structure for SAD/SSD calculation

17. Experimental Configuration
IntraPeriod : 32 # Period of I-Frame
GOPSize : 8 # GOP Size
QP : 32 # Quantization Parameter
FramesToBeEncoded : 100 # Number of frames to be coded
FrameRate : 60 # Frame Rate per second
Number of frames :100 # frames used per sequence
Intel COREi5, Windows 8 and 8GB RAM

18. Test sequences [8] BQSquare_416x240_60.yuv BQMall_832x480_60.yuv
Fig 11: Test sequences
BQTerrace_1920x1080_60.yuv

19. PSNR
Fig 12: PSNR comparison

20. Bit Rate
Fig 13: Bitrate comparison

21. Time
Fig 14: Time comparison

22. Comparison using BD-PSNR
Fig 15: BD-PSNR Comparison

23. Comparison using BD-Bitrate
Fig 15: BD-Rate Comparison

24. R-D Plot
Fig 16: R-D Plot

25. Conclusion
As proposed by implementing SIMD on various blocks of HEVC encoder there is significant optimization on time scale without affecting the throughput and quality of video. This result shows significant reduction in encoding time of test sequences due to optimization in motion vector calculation, Hadamard transform and SAD/SSD calculation.
It can observed from test results for PSNR comparison there is no significant reduction in quality of video as there is about 0.5dB reduction in PSNR which is tolerable. Bitrate of the optimized test sequence is also consistent as compared to original test sequences.
But it can be observed that there is major difference in encoding period of test sequences as there is lot of optimization done in calculation of motion vectors, Hadamard transform and SAD/SSD calculation in HEVC encoder which is the most time consuming block. SIMD instructions are used for all these calculation due to which processing time reduces to greater extent without affecting quality of video sequences.

26. Future Work
SIMD optimization can be future implemented on calculation of integer transform and RDOQ. Along with these, performing parallel programming on HEVC code can be implement using GPU.

27. Acronyms AVC: Advanced Video Coding
CABAC: Context-Adaptive Binary Arithmetic Coding
CB: Coding Block
CTB: Coding Tree Block
CTU: Coding Tree Unit
CU: Coding Unit
GPU: Graphical Processing Unit
HEVC: High Efficiency Video Coding
JCT-VC: Joint Collaborative Team on Video Coding
MC: Motion Compensation
ME: Motion Estimation
MOS: Mean Opinion Score
PB: Prediction Block

28. Acronyms PU: Prediction Unit
RDOQ: Rate Distortion Optimized Quantization
SAD: Sum of Absolute Differences
SAO: Sample Adaptive Offset
SATD: Sum of Absolute Transformed Differences (SATD)
SIMD: Single Instruction Multiple Data
SSD: Sum of Squared Difference
SSE: Streaming SIMD Extensions
TB: Transform Block
TU: Transform Unit

29. References
[1] G. J. Sullivan, J.-R. Ohm, W.-J. Han, and T. Wiegand, “Overview of the High Efficiency Video Coding (HEVC) standard,” IEEE Trans. Circuits Syst. Video Technol., vol. 22, no. 12, pp. 1648–1667, Dec [2] Keji Chen, Yizhou Duan, Leju Yan, Jun Sun and Zongming Guo, “Efficient SIMD Optimization of HEVC Encoder over X86 Processors ,” Institute of Computer Science and Technology, Peking University, Beijing , China. [3] JCT-VC, “HM6: High Efficiency Video Coding (HEVC) Test Model 6 Encoder Description,”JCTVC-H1002, Feb [4] D. Marpe et al., “Video compression using nested quadtree structures, leaf merging, and improved techniques for motion representation and entropy coding,” IEEE Trans. Circuits Syst. Video Technol., vol. 20, no. 12, pp –1687, Dec [5] Explanation of block partition:

30. References
[6] Intel Corp., Intel® 64 and IA-32 Architectures Software Developers Manual [7] Leju Yan; Yizhou Duan; Jun Sun; Zongming Guo , “Implementation of HEVC decoder on x86 processors with SIMD optimization,” VCIP, pp. 1-6, Nov [8] Test Sequence : ftp://ftp.tnt.uni-hannover.de/testsequences [9] HM9.2 Software: [10] BD Rate and BD PSNR Calculation : [11] SIMD implementation sample:

31. THANK YOU