1. 18/09/2006Wilco Vink / Martin van Beuzekom / Leo Wiggers L0 Workshop Pile-Up System

2. 18/09/2006Wilco Vink / Martin van Beuzekom / Leo Wiggers Pile-Up system Overview Where are we –Hybrid –Passive boards –Optical Tx Board –Veprob –Output board Latency Planning / PRR Commissioning –Timing parameters Beetle –Timing parameters Optical Tx Boards –Bcid labeling

3. 18/09/2006Wilco Vink / Martin van Beuzekom / Leo Wiggers Pile-Up dataflow All boards (proto-types) present for testing @Nikhef only currently under test Hybrids kapton cables repeater boards transition boards optical boards velo ctrl boards specs master ECS pvss, test software C UTB patterngen. VEPROB boards output board L0DU @IP8 default dataflow TTCvx VME cpu Analog Tell1 digital tell1 UTB databuffer VME cpu TTCvi Odin

4. 18/09/2006Wilco Vink / Martin van Beuzekom / Leo Wiggers Hybrids Beetle chips at Nikhef (v1.5) 3 Hybrids produced –1 delaminated during reflow soldering -> lost! –1 smd assembled –1 with beetle chips glued & control lines bonded (foto) 3,4 Hybrids in production, expected end October

5. 18/09/2006Wilco Vink / Martin van Beuzekom / Leo Wiggers Passive boards Kapton cables –Expected end October Repeater boards: 3 different types –1 type produced & tested –2 other types layout done Transition boards: 2 types –inner silicon strips, proto board used in test setup –outer silicon strips, layout in progress 6U vme 30x30 cm 20x75 cm

6. 18/09/2006Wilco Vink / Martin van Beuzekom / Leo Wiggers Optical Tx Board Optical board: –12 GOL –3 FPGA Sync/Mux logic Capture & align beetle binary data Assign Bcid to data –Tune parameters Clock delay (whole board) Alignment per databit, 4 phases Bcid label offset Slow control (i2c) via Velo control board, OK TFC via Velo control board, OK BERR test –OK –With optical attenuator: to be done Pattern testing in progress

7. 18/09/2006Wilco Vink / Martin van Beuzekom / Leo Wiggers VEPROB VEPROB proto in test setup Slow control (CCPC) OK –Dim server, Pvss panels needed Tests done: –Vertex finder algorithm via debug ram -> matches simulation results –Optical input links OK –BERR, without attenuator OK Tests in progress: –Vertex finder algorithm, pattern from pattern gen. via transition & optical Tx board –latency matches simulation & specs

8. 18/09/2006Wilco Vink / Martin van Beuzekom / Leo Wiggers Output Board FPGA coding done & simulated Schematic entry in progress Board items –9Ux400mm 2.4 mm 10 layer pcb –Xilinx Virtex 4 –4 serial inputs 1.6 Gb/s copper –2 optical serial outputs -> L0DU –CCPC / Glue Card –TTCrq Layout done in 4 weeks PVSS panels needed

9. 18/09/2006Wilco Vink / Martin van Beuzekom / Leo Wiggers VELO Control Board Design & production: CERN & Free University Amsterdam Supplies all TFC and slow control signals 3 VELO control boards used in Pile-Up –for 8 Optical tx Boards & –4 hybrids 1 proto-board in setup – Controlled via PVSS panels (supplied VELO group) –Additional PVSS panel for Pile-Up specific Beetle settings (comparator) needed

10. 18/09/2006Wilco Vink / Martin van Beuzekom / Leo Wiggers Latency from input optical Tx board to output of Veprob –Quoted latency (without trunk cable) 49 LHC clock cycles –Measured latency 42 LHC cycles Difference due to gain in algorithm –BUT: gain of 7 cycles partially lost due to Extra clock cycles in SERDES of Virtex4 (output board) Longer cables between VELO tank and balcony (~20 meters) –Loss < gain: quoted total latency still realistic Latency

11. 18/09/2006Wilco Vink / Martin van Beuzekom / Leo Wiggers Planning & towards PRR Hybrid deadline: VELO installation –2 hybrids: Jan 2007 (right detector halve) –2 hybrids: March 2007 (left detector halve) Optical TX Board + VEPROB –To be tested before PRR : BERR with attenuator Bit pattern testing Data flow to TELL1 Finished end Nov Output board: –Only 1 (+1) needed!, use prototype (if OK)

12. 18/09/2006Wilco Vink / Martin van Beuzekom / Leo Wiggers Overview Where are we –Hybrid –Passive boards –Optical Tx Board –Veprob –Output board Latency Planning / PRR Commissioning –Timing parameters Beetle –Timing parameters Optical Tx Boards –Bcid labeling

13. 18/09/2006Wilco Vink / Martin van Beuzekom / Leo Wiggers Commissioning Hybrids kapton cables repeater boards transition boards optical boards velo ctrl boards specs master ECS pvss, test software C VEPROB boards output board L0DU @IP8 TTCvx Analog Tell1 digital tell1 Odin Parameters: 1.TP amplitude, TP timing, comparator threshold, clk delay 2.“Sampling” moment, clk delay, Bcnt offset 3.L0 trigger yes/no Bcnt offset 12 3 default dataflow

14. 18/09/2006Wilco Vink / Martin van Beuzekom / Leo Wiggers System test/ Commissioning @Nikhef –System test with all board types (except L0DU) –Tune parameters: Beetle clocks & thresholds Optical Tx board clocks Veprob’s & output board “auto sync” on Bcid (no timing par.) @IP8 –System test with all boards (simultaneously) –Output board to L0DU links –Retune timing parameters (different cables) –With beam Retune Beetle thresholds (Common mode noise) Tune Beetle timing (x-ing) Remaining (free) parameter: Bcid offset on Optical Tx boards To be tuned w.r.t. Calo, Muon… Lumi run –Check synchronicity continuously in hardware Link syncs Lowest bits of Bcid (on VEPROBS) Consecutive Bcids on output board

15. 18/09/2006Wilco Vink / Martin van Beuzekom / Leo Wiggers Beetle testpulse Var. testpulse amplitude -> long Time over threshold var. testpulse timing settings via VELO control board with statistics thr*timing fine tuning threshold time over thr. Comparator clk Beetle Beetle out Shaper out TestPulse To analog Tell1 To Pile-Up System Comparator threshold TP amplitude

16. 18/09/2006Wilco Vink / Martin van Beuzekom / Leo Wiggers Optical station Tune input sampling until all hits end up in one BCID Add Bcid label to data Coarse timing via clock selection Fine tuning of clock phase in 0.5ns steps (VELO control board) Fine tuning via histogramming DFF D clka clkb clka clkb clkselect(0) clkselect(1) clka clkb Beetle data ff1ff2ff3 Fine tune clk delay (control board)

17. 18/09/2006Wilco Vink / Martin van Beuzekom / Leo Wiggers Resets Beetle pipeline: L0FE rst Bcid labeling in Optical station: BxRst L0 yes/no counters in Veprobs: L0FE rst

18. 18/09/2006Wilco Vink / Martin van Beuzekom / Leo Wiggers

19. 18/09/2006Wilco Vink / Martin van Beuzekom / Leo Wiggers Sync Optical Tx Brd -> VEPROB 8 Optical Tx boards synced with L0FE reset lock receivers at de-asserted RxDv: last events(1-31) of bunch count cycle are idles, length programmable via ECS data marked with LSB/MSB bit and B-ID each 3 rd link contains B-ID VEPROB input links (24/Brd) are synced on LSB/MSB and B-ID(0) bits

20. 18/09/2006Wilco Vink / Martin van Beuzekom / Leo Wiggers Beetle testpulse threshold time over thr. LHC clk beetle Beetle out Shaper out TestPulse Data in Veprob L0 yes (16 consecutive) Tune latency trigger until data in raw buffer

21. 18/09/2006Wilco Vink / Martin van Beuzekom / Leo Wiggers TELL1 Analog TELL1 –Identical to VELO –PVSS software by VELO Digital TELL1 –FPGA coding by Guido –Output data format VEPROB changed (alike ST format) –PVSS software: Based on other TELL1 PVSS software Modifications by Pile-Up group –Needed for tuning (RAW data buffer) VEPROB TELL1 Raw data buffer dummy12dummy 13dummy 15 dummy 14 dummy New dataflow for four consecutive triggers

22. 18/09/2006Wilco Vink / Martin van Beuzekom / Leo Wiggers Latency LHC Clocks spec / sim measured Hybrid 50ns2 Cabling to optical station18 m (5ns/m)108 ns5 VETO Optical Station Synchronisation and demultiplexing 4 GOL 64 ns max3 Optical Ribbon 52m (old:60m) (4.5ns/m) 260 ns11 (4m ribbon) Vertex processor board Orx-card(tlk2501) 4 43 channel sync and vertex finder algoritm(xilinx FPGA) 875ns35 (was 42) MGT Rocket i/o transmitter + cable 4 Output board MGT Rocket i/o receiver 4 Mux 1 MGT Rocket i/o transmitter 3 Cable to L0DU 90ns4 Total: 84(87)

23. 18/09/2006Wilco Vink / Martin van Beuzekom / Leo Wiggers Commissioning Pile-Up system control –Needed TFC (odin + ttcvx) PVSS controlled ?? –ECS software needed Configure VEPROBs + Digital TELL1 –ECS software needed –Test access to RAW data buffer Optical link test optical station -> VEPROB –“self test”, only ECS software needed to read status Fine tune Beetle timing parameters (VELO control board) –Find peak timing of beetle Tune Beetle comparator threshold via threshold scan –ECS + access to RAW data buffer –Histogramming / fitting on ?? farm node Tune timing of optical station –Generate pattern with beetle test-pulse –Capture data with VEPROB/TELL1 –Tune synchronization stage in optical boards until ALL “hits” end up in ONE BCID –ECS software + Access to RAW data buffer needed –Histogramming on ?? farm node Check communication VEPROB -> Output board –ECS to check status register

24. 18/09/2006Wilco Vink / Martin van Beuzekom / Leo Wiggers Pile-Up System overview RAW Buffer

25. 18/09/2006Wilco Vink / Martin van Beuzekom / Leo Wiggers Hybrid Configuration via SPECS on VELO Control Board -> I2C –4 hybrids, each: 16 Beetles, each: –18 Bytes registers –2 X 16 Byte registers –128 Bytes comparator thresholds Total: ~ 11k Byte Configuration time: seconds FSM: Trigger & DAQ Domain PVSS software by VELO group –Maybe small modifications for comparator specific registers

26. 18/09/2006Wilco Vink / Martin van Beuzekom / Leo Wiggers Planning 2006 2007

27. 18/09/2006Wilco Vink / Martin van Beuzekom / Leo Wiggers Hybrids Beetle chip selection done –Chips at Nikhef (v1.5) 2 Hybrids production done –1 hybrid assembly in progress –1 hybrid assembly & bonding done (foto) 3,4 Hybrids in production expected end October Kapton Cables(4) Repeater Boards(12) Velo tank

28. 18/09/2006Wilco Vink / Martin van Beuzekom / Leo Wiggers Passives ?? Cables Kapton cables –Expected end October Repeater boards 3 versions –Version b layout in progress –Version c proto assembly in progress –Version d ready for production Transition Boards: 2 versions –Version: inner strips 1 proto in test setup –Version: outer strips layout in progress Kapton Cables(4) Repeater Boards(12) Velo tank Kapton Cables(4) Transition Boards(8) 256 cat5 Optical station crate Custom backplane Optical Boards(8) vacuum feed through