1. The Assemble, Unassemble commands of the debugger: U Command for converting machine code language source Equivalent machine code instructions Equivalent assembly statements A command for converting assembly statements

2. The Go command of the debugger: Format G =[starting address] [breakpoint address] Execute the instructions from the starting address till the breakpoint address appears in the IP register (address of the instruction following the end of the program)

3. Unsigned Multiplication Format MUL S S is the source: R 8 or R 16, M 8 or M 16 Action [AL] * [S 8 ] [AX] [AX] * [S 16 ] [DX]:[AX] Affects all flags

4. Signed Multiplication Format IMUL S S is the source: R 8 or R 16, M 8 or M 16 Action [AL] * [S 8 ] [AX] [AX] * [S 16 ] [DX]:[AX] Affects all flags

5. MOV AL, FF MOV CL,FE MUL CL [AX] = FD02 16 = 64770 10 MOV AX, 00FF MOV CX,00FE IMUL CL [AL] = 255 10 [CL] = 254 10 Unsigned multiplication Signed multiplication [AX] = 0002 16 = 2 16 [AL] = -1 10 [CL] = -2 10

6. MOV AL, 09 MOV CL, 08 MUL CL [AX] = 48 H AAM Adjust AL after multiplication Q(AL 10 ) / 10 AH R(AL 10 ) / 10 AL Affects all flags BCD Arithmetics [AX] = 0702 Result is unpacked BCD

7. Unsigned Division Format DIV S S is the source: R 8 or R 16, M 8 or M 16 Action Q([AX] / [S 8 ]) [AL] R([AX] / [S 8 ]) [AH] If Q is ≥ FF then type 0 interrupt occurs Q(([AX]:[DX]) / [S 16 ]) [AX] R(([DX]:[AX]) / [S 16 ]) [DX] If Q is ≥ FFFF then type 0 interrupt occurs Affects all flags

8. Signed Division Format IDIV S S is the source: R 8 or R 16, M 8 or M 16 Action Q([AX] / [S 8 ]) [AL] R([AX] / [S 8 ]) [AH] If Q is ≥ 7F then type 0 interrupt occurs Q(([AX]:[DX]) / [S 16 ]) [AX] R(([DX]:[AX]) / [S 16 ]) [DX] If Q is7FFF then type 0 interrupt occurs Affects all flags

9. AAD Adjust AX for division This instruction assumes that AH and AL contain unpacked DCD numbers MOV AX,0702 AAD Action: [AH] 10 * 10 + [AL] 10 [AL] 00 [AH] [AL] 10 [AL] 16 This instruction does the opposite of AAM

10. MOV AX, 314E 314E 16 = 12622 10 MOV BL,40 40 16 = 64 10 IDIV BL quotient = 197 10 quotient > 127 10 or 7F 16 divide overflow MOV AX, 0010 10 16 = +16 10 MOV BL,FD FD 16 = -3 10 IDIV BL quotient in AL [AL] = -5 10 = FB 16 residue in AH [AH] = 1 10 = 1 16

11. MOV AX, 3149 [AX] 10 = 12617 MOV BL,04 quotient = 3154 quotient > 255 10 or FF 16 DIV BL divide overflow MOV AX, 314E 314E 16 = 12622 10 MOV BL,40 40 16 = 64 10 DIV BL quotient in AL [AL] = 197 10 = C5 16 residue in AH [AH] = 14 10 = E 16

12. CBW convert byte to word Action most significant bit of AL all bits of AH does not affect any flag CWD convert word to double word Action most significant bit of AX all bits of DX does not affect any flag

13. MOV AL, 81 [AX] = 0081 16 CBW [AX] = FF81 16 CWD [DX] = FFFF 16 : [AX] = FF81 16

14. The Compare Instruction Format CMP D, S Effect Affects all flags Subtraction using 2’s complement MOV AH, 00 SAHF MOV AL, 99 [AL] = 10011001 2 -ve 2’s complement 01100111 2 = - 67 16 = - 103 10 MOV BL, 1B [BL] = 00011011 2 +ve = 27 10 2’s complement 11100101 2 CMP AL, BL 10011001+ 11100101 = 01111110 -103 10 – 27 10 = -130 10 OV, PL, NZ, AC, PE, NC Overflow, positive, not zero, auxiliary carry, parity even, no carry DS Register Memory Register Immediate MemoryImmediate AccumulatorImmediate

15. Flag Control Instructions MnemonicMeaningOperationFlags Affected LAHF Load AH from flags [AH] [flags] None SAHF Store AH into flags [flags] [AH] SF, ZF, AF, PF, CF CLC Clear Carry flag [CF] 0 CF STC Set Carry flag [CF] 1 CF CMC Complement carry flag [CF] CF CLI Clear Interrupt flag [IF] 0 IF STI Set Interrupt flag [IF] 0 IF

16. MOV AH, 00 SAHF MOV AX, 1234 [AX] = 0001 0010 0011 0100 2 +ve = +4660 10 MOV BX, 0ABCD [BX] = 1010 1011 1100 1101 2 -ve 2’s complement 0101 0100 0011 0011 2 [BX] = - 21555 10 CMP AX, BX 0001 0010 0011 0100 2 + 0101 0100 0011 0011 2 = 0110 0110 0110 0111 2 +4660 10 – ( - 21555 10 ) No overflow, Auxiliary carry, Carry, Not zero, Positive, Odd parity NV AC CY PL NG PO SF CF PF AF ZF X X X

17. Logic Instructions No Flags [D] [D]NOT D All Flags[S] + [D] [D]XOR D,S All Flags[S] + [D] [D]OR D,S All Flags[S]. [D] [D]AND D,S Flags Affected OperationFormat immediate Acc immediate M R RM MR RR SD

18. MOV AX,0055 [AL] = 01010101 2 = 55 16 AND AL,1F 01010101.00011111 [AL] = 00010101 2 = 15 16 OR AL,C0 00010101 +11000000 [AL] = 11010101 2 = D5 16 XOR AL,0F 11010101 +00001111 [AL] = 11011010 2 = DA 1 NOT AL [AL] = 00100101 2 = 25 16

19. Shift Instructions: SHL shift logical left format SHL D, Count Example: SHL AX,1 D Count register 1 CL memory 1 CL 0 0 0 0 0 0 1 1 0 0 1 0 1 0 1 0 0 0 1 0 1 0 0 0 0 1 1 1 0 00 0 CF 0 0 1234 16 2468 16

20. SHR shift logical right format SHL R, Count Example: SHR AX,CL [CL] = 2 SAR AX,CL [CL] = 2 0 0 0 0 0 0 1 1 0 0 1 0 1 0 1 0 0 0 0 0 1 0 0 0 1 0 0 1 1 10 0 CF 00 1234 16 048D 16 091A 16 0 0 0 1 0 10 0 0 0 0 10 0 1 1 0 0 0 0 0 0 0 1 0 1 0 0 1 00 1 CF 1 0246 16

21. Rotate Instructions: ROL D, Count ROL AX, 1 CF 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 1 0 0 0 1 0 1 0 0 0 0 1 1 1 0 00 0 1234 16 2468 16 0 0 0 0 0 0 1 1 0 0 1 0 1 0 1 0 0 1 0 0 0 1 0 0 00 1 0 0 10 1 1234 16 4123 16 ROR AX, CL [CL] = 4 CF 0

22. RCL D, Count RCL AX, CL [CL] = 4 0 0 0 0 0 0 1 1 0 0 1 0 1 0 1 0 CF 0 Before execution [AX] = 1234 16 0 0 1 0 0 1 0 1 01 0 0 0 0 0 0 CF 1 After execution [AX] = 23 40 16

23. RCR D, Count RCR AX, CL [CL] = 4 0 0 0 0 0 0 1 1 0 0 1 0 1 0 1 0 CF 0 Before execution [AX] = 1234 16 1 0 0 0 0 1 0 0 00 1 0 0 1 0 1 CF 0 After execution [AX] = 81 23 16