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High-Speed Circuit-Tuning Techniques Based on Lagrangian Relaxation Charlie Chung-Ping Chen ICCAD 99’ Embedded Tutorial Session 12A chen@engr.wisc.edu (608)2651145

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C. Chen, ICCAD ‘99 Embedded Tutorial, Session 12A High-Speed Circuit-Sizing Techniques based on Lagrangian Relaxation People Involved Joint work Charlie Chen, University of Wisconsin at Madison Chris Chu, Iowa State University D. F. Wong, University of Texas at Austin Publication “Fast and Exact Simultaneous Gate and Wire Sizing by Lagrangian Relaxation”, IEEE Transactions on Computer-Aided Design, July 1999

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C. Chen, ICCAD ‘99 Embedded Tutorial, Session 12A High-Speed Circuit-Sizing Techniques based on Lagrangian Relaxation Acknowledgement Strategic CAD Labs, Intel Corp. Steve Burns, Prashant Sawkar, N. Sherwani, and Noel Menezes IBM T. J. Watson Center Chandu Visweswariah C. Kime, L. He (UWisc-Madison)

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C. Chen, ICCAD ‘99 Embedded Tutorial, Session 12A High-Speed Circuit-Sizing Techniques based on Lagrangian Relaxation Outline Motivation Overview of Circuit Tuning Techniques Lagrangian Relaxation Based Circuit Tuning

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C. Chen, ICCAD ‘99 Embedded Tutorial, Session 12A High-Speed Circuit-Sizing Techniques based on Lagrangian Relaxation Motivation Double the work load and design complexity every 18 months

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C. Chen, ICCAD ‘99 Embedded Tutorial, Session 12A High-Speed Circuit-Sizing Techniques based on Lagrangian Relaxation Motivation Trends –Increased custom design –Aggressive tuning for performance improvement –Shorter time to market –Interconnect effects severe –Signal integrity issues emerging Circuit Tuning –Can significantly improve circuit performance and signal integrity without major modification

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C. Chen, ICCAD ‘99 Embedded Tutorial, Session 12A High-Speed Circuit-Sizing Techniques based on Lagrangian Relaxation Manual Sizing Pros –Takes advantage of human experience –Reliable –Simultaneously combines with other optimization techniques directly Cons –Slow, tedious, limited, and error-prone procedure –Rely too much on experience, requires solid training –Optimality not guaranteed (don’t know when to stop) Change Satisfy? 1000+ iterations Simulate

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C. Chen, ICCAD ‘99 Embedded Tutorial, Session 12A High-Speed Circuit-Sizing Techniques based on Lagrangian Relaxation Automatic Circuit Tuning Pros –Fast –Achieves the best performance with interconnect considerations –Explores alternatives (power/delay/noise tradeoff) –Boosts productivity –Optimality guaranty (for convex problems) –Insures timing and reliability Cons –Complicated tool development and support ($$) –Tool testing, integration, and training

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C. Chen, ICCAD ‘99 Embedded Tutorial, Session 12A High-Speed Circuit-Sizing Techniques based on Lagrangian Relaxation Good Tuning Algorithm Fast Optimality guaranteed (for convex problem) Versatile Easy to use Solution quality index (error bound to the optimal solution) Simple (Easy to develop and maintain)

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C. Chen, ICCAD ‘99 Embedded Tutorial, Session 12A High-Speed Circuit-Sizing Techniques based on Lagrangian Relaxation Static vs. Dynamic Sizing Static Sizing –Stage Based –Nature circuit decomposition, large scale tuning capability –Very reasonable accuracy (when using good model) –No need for sensitization vectors –Solves for all critical paths in a polynomial formulation –False paths; Potentially inaccurate modeling of slopes of input excitation Dynamic Sizing –Simulation based –More accurate –No false path problems –Need good input vectors; good for circuits for which critical paths are known and limited –Takes care of a few scenario only –Relatively slower

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C. Chen, ICCAD ‘99 Embedded Tutorial, Session 12A High-Speed Circuit-Sizing Techniques based on Lagrangian Relaxation A Simple Sizing Problem maxMinimize the maximum delay D max by changing w 1,…,w n w1w1w1w1 w2w2w2w2 w9w9w9w9 w 10 w 11 w6w6w6w6 w8w8w8w8 w3w3w3w3 w5w5w5w5 w4w4w4w4 w7w7w7w7 D 1 <D max D 2 <D max a b

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C. Chen, ICCAD ‘99 Embedded Tutorial, Session 12A High-Speed Circuit-Sizing Techniques based on Lagrangian Relaxation Existing Sizing Works Algorithm: fast, non-optimal for general problem formulation –TILOS (J. Fishburn, A. Dunlop, ICCAD 85’) –Weight Delay Optimization (J. Cong et al., ICCAD 95’) Mathematical Programming: slower, optimal –Geometrical Programming (TILOS) –Augmented Lagrangian (D. P. Marple et al., 86’) –Sequential Linear Programming (S. Sapatnekar et al.) –Interior Point Method (S. Sapatnekar et al., TCAD 93’) –Sequential Quadratic Programming (N. Menezes et al., DAC 95’) –Augmented Lagrangian + Adjoin Sensitivity (C. Visweswariah et al., ICCAD 96’, ICCAD97’) Is there any method that is fast and optimal?

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C. Chen, ICCAD ‘99 Embedded Tutorial, Session 12A High-Speed Circuit-Sizing Techniques based on Lagrangian Relaxation Converge? Mathematical Programming Algorithm ? SLP SQP Augmented Lagrangian TILOS Weighted Delay FastOptimal

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C. Chen, ICCAD ‘99 Embedded Tutorial, Session 12A High-Speed Circuit-Sizing Techniques based on Lagrangian Relaxation Heuristic Approach TILOS: (J. Fishburn etc ICCAD 85’) –Find all the sensitivities associated with each gate –Up-Size one gate only with the maximum sensitivity –To minimize the object function w4w4w4w4 w 11 w1w1w1w1 w5w5w5w5 w7w7w7w7 w9w9w9w9 w8w8w8w8 w 10 w6w6w6w6 w3w3w3w3 w2w2w2w2 D 1 <D max D 2 <D max Minimize D max a b

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C. Chen, ICCAD ‘99 Embedded Tutorial, Session 12A High-Speed Circuit-Sizing Techniques based on Lagrangian Relaxation Weighted Delay OptimizationDrivers Loads J. Cong ICCAD 95’ –Size one wire at a time in DFS order –To minimize the weighted delay –best weight? w3w3w3w3 w5w5w5w5 w4w4w4w4 w1w1w1w1 w2w2w2w2 1 D 1 1 D 1 2 D 2 2 D 2 Minimize 1 D 1 2 D 2

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C. Chen, ICCAD ‘99 Embedded Tutorial, Session 12A High-Speed Circuit-Sizing Techniques based on Lagrangian Relaxation Mathematical Programming Problem Formulation: Lagrangian: Optimality (Necessary) Condition: (Kuhn-Tucker Condition)

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C. Chen, ICCAD ‘99 Embedded Tutorial, Session 12A High-Speed Circuit-Sizing Techniques based on Lagrangian Relaxation PSLP v.s. SQP Penalty Sequential Linear Programming Sequential Quadratic Programming

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C. Chen, ICCAD ‘99 Embedded Tutorial, Session 12A High-Speed Circuit-Sizing Techniques based on Lagrangian Relaxation Lagrangian Methods Augmented Lagrangian Lagrangian Relaxation

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C. Chen, ICCAD ‘99 Embedded Tutorial, Session 12A High-Speed Circuit-Sizing Techniques based on Lagrangian Relaxation Lagrangian Relaxation Theory LRS (Lagrangian Relaxation Subproblem) There exist Lagrangian multipliers will lead LRS to find the optimal solution for convex programming problem The optimal solution for any LRS is a lower bound of the original problem for any type of problem

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C. Chen, ICCAD ‘99 Embedded Tutorial, Session 12A High-Speed Circuit-Sizing Techniques based on Lagrangian Relaxation Lagrangian Relaxation

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C. Chen, ICCAD ‘99 Embedded Tutorial, Session 12A High-Speed Circuit-Sizing Techniques based on Lagrangian Relaxation Lagrangian Relaxation SLP SQP Augmented Lagrangian TILOS Weighted Delay Mathematical Programming Algorithm Lagrangian Relaxation

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C. Chen, ICCAD ‘99 Embedded Tutorial, Session 12A High-Speed Circuit-Sizing Techniques based on Lagrangian Relaxation Lagrangian Relaxation Framework Update Multipliers Weighted Delay Optimization Converge?

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C. Chen, ICCAD ‘99 Embedded Tutorial, Session 12A High-Speed Circuit-Sizing Techniques based on Lagrangian Relaxation Lagrangian Relaxation Framework D1D1D1D1 D2D2D2D2 D max D1D1D1D1 D2D2D2D2 D1D1D1D1 D2D2D2D2 1 2 1 2 More Critical -> More Resource -> More Weight

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C. Chen, ICCAD ‘99 Embedded Tutorial, Session 12A High-Speed Circuit-Sizing Techniques based on Lagrangian Relaxation Weighted Minimization Traverse the circuit in topological order Resize each component to minimize Lagrangian during visit w2w2w2w2 w3w3w3w3 w1w1w1w1 D1D1D1D1 D2D2D2D2 a b Minimize 1 D 1 2 D 2

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C. Chen, ICCAD ‘99 Embedded Tutorial, Session 12A High-Speed Circuit-Sizing Techniques based on Lagrangian Relaxation Multipliers Adjustment a subgradient approach Subgradient: An extension definition of gradient for non- smooth function Experience: Simple heuristic implementation can achieve very good convergence rate Reference: Non-smooth function optimization: N. Z. Shor

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C. Chen, ICCAD ‘99 Embedded Tutorial, Session 12A High-Speed Circuit-Sizing Techniques based on Lagrangian Relaxation Path Delay Formulation d1d1d1d1 d2d2d2d2 d3d3d3d3 D1D1D1D1 D2D2D2D2 AaAaAaAa AbAbAbAb AcAcAcAc Exponential growing More accurate Can exclude false paths

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C. Chen, ICCAD ‘99 Embedded Tutorial, Session 12A High-Speed Circuit-Sizing Techniques based on Lagrangian Relaxation Stage Delay Formulation d1d1d1d1 d2d2d2d2 d3d3d3d3 D1D1D1D1 D2D2D2D2 AaAaAaAa AbAbAbAb AcAcAcAc AeAeAeAe Polynomial size Less accurate Contains false paths

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C. Chen, ICCAD ‘99 Embedded Tutorial, Session 12A High-Speed Circuit-Sizing Techniques based on Lagrangian Relaxation Compatible? Stage Based Path Based ?

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C. Chen, ICCAD ‘99 Embedded Tutorial, Session 12A High-Speed Circuit-Sizing Techniques based on Lagrangian Relaxation Both Multipliers Satisfy KCL (Flow Conservation) 1 2 3 4 5 43 43 32 32 31 31 53 53 43 53 31 32 43 53 31 32 1 2 4 5 3,in 3,out 3,in 3,out 41 41 42 42 51 51 52 52 3 Path Based Stage Based

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C. Chen, ICCAD ‘99 Embedded Tutorial, Session 12A High-Speed Circuit-Sizing Techniques based on Lagrangian Relaxation Mixed Delay Formulation Path Based Stage Based Stage Based

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C. Chen, ICCAD ‘99 Embedded Tutorial, Session 12A High-Speed Circuit-Sizing Techniques based on Lagrangian Relaxation Compatible? Stage Based Path Based Lagrangian Relaxation

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C. Chen, ICCAD ‘99 Embedded Tutorial, Session 12A High-Speed Circuit-Sizing Techniques based on Lagrangian Relaxation Hierarchical Objective Function Decomposition Divide the Lagrangian into who terms (containing or not containing variable w i ) Hierarchically update the Lagrangian during resizing

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C. Chen, ICCAD ‘99 Embedded Tutorial, Session 12A High-Speed Circuit-Sizing Techniques based on Lagrangian Relaxation Intermediate Variables Cancellation D1D1D1D1 D2D2D2D2 AaAaAaAa AbAbAbAb AcAcAcAc AeAeAeAe ae ae be be e1 e1 e2 e2 c2 c2 ae + be = e1 + e2 ae + be = e1 + e2 + ae + be + e1 - + e2 - ae (A a + d 1 ) + be (A b + d 1 ) + e1 (d 2 - D 1 ) + e2 (d 3 - D 2 )

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C. Chen, ICCAD ‘99 Embedded Tutorial, Session 12A High-Speed Circuit-Sizing Techniques based on Lagrangian Relaxation Decomposition and Pruning Flow Decomposition Prune out all the gates with zero multipliers

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C. Chen, ICCAD ‘99 Embedded Tutorial, Session 12A High-Speed Circuit-Sizing Techniques based on Lagrangian Relaxation Complimentary Condition Implications i imax i (D i -D max )= 0 Optimal Solution i max – Critical Path, weight i >= 0.0, path delay=D max – i max – Non-critical path, weight i = 0.0, path delay < D max

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C. Chen, ICCAD ‘99 Embedded Tutorial, Session 12A High-Speed Circuit-Sizing Techniques based on Lagrangian Relaxation Convergence Sequence Lagrangian=Lower Bound Weighted Delay<=Maximum Delay Any Feasible Maximum Delay= Upper Bound Optimal Solution # Iteration Max Delay

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C. Chen, ICCAD ‘99 Embedded Tutorial, Session 12A High-Speed Circuit-Sizing Techniques based on Lagrangian Relaxation Transistor Sizing Extension

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C. Chen, ICCAD ‘99 Embedded Tutorial, Session 12A High-Speed Circuit-Sizing Techniques based on Lagrangian Relaxation Runtime and Storage Requirement

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C. Chen, ICCAD ‘99 Embedded Tutorial, Session 12A High-Speed Circuit-Sizing Techniques based on Lagrangian Relaxation Runtime versus Circuit Size

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C. Chen, ICCAD ‘99 Embedded Tutorial, Session 12A High-Speed Circuit-Sizing Techniques based on Lagrangian Relaxation Storage versus Circuit Size

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C. Chen, ICCAD ‘99 Embedded Tutorial, Session 12A High-Speed Circuit-Sizing Techniques based on Lagrangian Relaxation Convergence of Subgradient Optimization

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C. Chen, ICCAD ‘99 Embedded Tutorial, Session 12A High-Speed Circuit-Sizing Techniques based on Lagrangian Relaxation Area vs. Delay Tradeoff Curve

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C. Chen, ICCAD ‘99 Embedded Tutorial, Session 12A High-Speed Circuit-Sizing Techniques based on Lagrangian Relaxation Conclusion Lagrangian Relaxation –General mathematical programming algorithm –Optimality guarantee for convex programming problem –Versatile –No extra complication (no quadratic penalty function) –Lagrangian multiplier provides connections between mathematical programming and algorithmic approaches –Multipliers satisfy KCL (flow conservation) –Hierarchical update objective function provides extreme efficiency –Solution quality guaranteed (by providing lower bound)

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