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Combinational Circuit Design. Digital Circuits Combinational CircuitsSequential Circuits Output is determined by current values of inputs only. Output.

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Presentation on theme: "Combinational Circuit Design. Digital Circuits Combinational CircuitsSequential Circuits Output is determined by current values of inputs only. Output."— Presentation transcript:

1 Combinational Circuit Design

2 Digital Circuits Combinational CircuitsSequential Circuits Output is determined by current values of inputs only. Output is determined in general by current values of inputs and past values of inputs/outputs as well.

3 Design of Complex Combinational circuits Truth table has 2 16 entries System Description Truth Table Boolean expression Minimized Boolean expression Gate Netlist This design approach becomes difficult to use

4 Design system as a network of sub-systems that are of manageable size and can be implemented using the earlier approach of truth table, minimization etc.

5 General Approach System Sub-system-1 Sub-system-2 Sub-Sub-system-2 There are certain sub-systems or blocks that are used quite often such as : 1.decoders, encoders 2.Multiplexers 3.Adder/Subtractors, Multipliers 4.Comparators 5.Parity Generators 6.……..

6 Decoders Maps a smaller number of inputs to a larger set of outputs in general Active Low

7 Example

8 Decoder with Enable Input

9 Decoder: gate Implementation

10 A n to 2 n decoder is a minterm generator It can be used to implement any combinational circuit 1010 01000100 1

11 Implementation of a 3-variable function with a 3-to-8 decoder 0 000000 0 1 1 1 1 1 1 1 1 Although it is easy to implement any combinational circuit with this method, it is often very inefficient in terms of gate utilization. Note that this method does not require any minimization.

12 Implementing larger decoders using simpler ones. 3/8 decoder using 2/4 decoders E C0C0 How many 2/4 decoders are required to implement a 4/16 decoder ?

13 1 0 1 0 0 0 0 0 1010 0 0 1 0

14 Seven segment decoder 5 5 5 5 5 0 5

15

16 7449 BCD to seven segment decoder

17 Encoders An encoder performs the inverse operation of a decoder.

18

19 Priority Encoders printer D0D0 D1D1 D2D2 D3D3 Priority is 3,2,1,0 with user 3 having the highest priority X, Y have to be determined based on this priority order and the requests to use the resource.

20 Codes decimalNatural Binary Gray 00000 10001 200100011 3 0010 401000110 501010111 601100101 701110100 810001100 910011101 1010101111 1110111110 1211001010 1311011011 1411101001 1511111000 1-bit change as one goes from one code word to the next. 0111-1111-1000 0111-0000-1000 In the case of natural binary code: In the case of Gray code, no such problem occurs.

21 ASCII: American Standard Code for information interchange

22 Parity Extra bits are added to aid in error detection and correction decimalBinaryEven parity Odd parity 000000000001 100100110010 201001010100 301101100111 410010011000 510110101011 611011001101 711111111110 A 1-bit error changes the parity and thus can be detected

23 Multiplexers 0 1 0 I0I0 0 I0I0

24

25 Mux is often used when resources have to be shared 00 a c = a+c

26 Implementing Boolean expressions using Multiplexers ? ? 000 011 y = x 2 when x 1 = 0 x2x2 101 110 y = x 2 when x 1 = 1 x2x2

27 A 3 variable function can be implemented with a 4:1 mux with 2 select lines yz 0 00 10 F = 0 when yz = 00 0 0 1 01 10 F = x when yz =01 x 1 0 01 11 F = 1 when yz = 10 1 1 00 11 F = x when yz = 11 x Mux is more efficient way of implementing combinational circuits as compared to decoders.

28 Mux. expansion 0 1 0 0 1 I1I1 I1I1

29 1 0 1 0 1 I3I3 I3I3

30 DeMultiplexer

31 Demultiplexer is very much like a decoder 0 1 0 Data 1 0 0 0

32 Comparator

33 A>B A = B

34 Adder/Subtractor

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36 4-bit Adder A0A0 B0B0 0 S0S0 C1C1 A1A1 B1B1 S1S1 C2C2 A2A2 B2B2 S2S2 C3C3 A3A3 B3B3 S3S3 C4C4 Ripple Carry Adder (20 gate circuit)

37 Subtraction A - B = A + 2’s complement of B A - B = A + 1’s complement of B+1 A - B = A + B+1 One needs add a circuit for predicting errors resulting from overflow

38 Adder/Subtractor

39 Multiplier B 1 B 0 A 1 A 0 A 0 B 1 A 0 B 0 A 1 B 1 A 1 B 0 multiplicand multiplier Partial products C3 C2 C 1 C 0


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