1. 240-334 By Wannarat 240-334 Computer System Design Lecture 4 Wannarat Suntiamorntut

2. 240-334 By Wannarat Part I : Single Data Path

3. 240-334 By Wannarat Outline Design a Processor step by step Requirement of instruction set Components and clocking Testing Datapath Control Datapath

4. 240-334 By Wannarat Five Component of Computer Datapath Control Processor MEMORYMEMORY Input Output

5. 240-334 By Wannarat Performance Perspective Performance of machine is determined by CPI Processor Design : clock cycle time clock per instruction Single cycle processor : adv. : one clock cycle per instruction disadv. : long cycle time

6. 240-334 By Wannarat Design Processor Step by Step 1. Analyze instruction set ==> Datapath requirement 2. Selection Set of datapath and establish clocking methodology 3. Assembly datapath meeting requirement 4. Analyze implementation of each instruction to determine setting of control 5. Assembly the control logic

7. 240-334 By Wannarat MIPS Instruction Format

8. 240-334 By Wannarat Step 1 ADDUrd, rs, rtSUBU rd, rs, rt ORI rt, rs, imm16

9. 240-334 By Wannarat Step 1 lw rt, rs,imm16 sw rt, rs, imm16 beq rs, rt, imm16

10. 240-334 By Wannarat RTL All instructions start by fetching Mem[PC] ADDU rd <= rs + rt;PC = PC + 4 SUBU rd <= rs + rt;PC = PC + 4 Ori rt <= rs + zero_ext(imm16);PC = PC + 4 LOAD rt <= mem[rs] + sign_ext(imm16); PC=PC + 4 STORE mem[rs] + sign_ext(imm16)<=rt; PC=PC+4 BEQ if rs = rt then PC=PC+sign_ext(imm16)||00 else PC = PC + 4

11. 240-334 By Wannarat Step 1 : The requirement from instruction Memory Data & Instruction Register (32 x 32) Read rsRead rt Write rt or rd PC Extender Add and sub register or extend immediate Add 4 or extended immediate to PC

12. 240-334 By Wannarat Step 2 : Components of datapath Combination Element Storage elements Clocking methodology

13. 240-334 By Wannarat Combination Elements AdderMUX

14. 240-334 By Wannarat Combination Elements ALU

15. 240-334 By Wannarat Storage Element : Register Similar to D-flip/flop Write enable negated(0) : Data out won’t change asserted(1) : Data out will be data in

16. 240-334 By Wannarat Register file Consist of 32 registers Ra select register to bus A Rb select register to bus B Rw select register to be written via bus W

17. 240-334 By Wannarat Storage : Ideal Memory One Input One Output Memory word is selected by Address, Write enable = 1 then the data will be written Clock input : is a factor only during write operation During read operation : behaves on combination logic.

18. 240-334 By Wannarat Clock Methodology

19. 240-334 By Wannarat Step 3 : Register Transfer Requirements --> Datapath Assembly Instruction Fetch Read Operands and Execute Operation

20. 240-334 By Wannarat Step 3 a : Instruction Fetch Unit Update PC : Sequence Code: PC <= PC + 4 Branch and Jump : PC <- something else

21. 240-334 By Wannarat Step 3b : Add & Sub

22. 240-334 By Wannarat Register-Register Timing

23. 240-334 By Wannarat Step 3c :Logical Operations with Immed.

24. 240-334 By Wannarat Step 3d: Load operations

25. 240-334 By Wannarat Step 3e : Store Operations

26. 240-334 By Wannarat Step 3f: Branch instruction beq rs, rt, imme16 mem[pc] equal <= rs = rt if (con eq 0) then PC<=PC+4+(signExt(imm16)x4); else PC <= PC + 4;

27. 240-334 By Wannarat Datapath for Branch Operations

28. 240-334 By Wannarat Put it all together

29. 240-334 By Wannarat Abstract view of critical path

30. 240-334 By Wannarat Step 4 : Control Path

31. 240-334 By Wannarat Meaning of control signal Rs, Rt and Imme16 hardwire to datapath nPC_sel : 0 => PC PC PC PC <= PC + 4 + signExt(Imm16) || 00

32. 240-334 By Wannarat Meaning of control signals ExtOp : Zero, signMemWr:write memory ALUsrc: 0=>regB, 1=>imme Memtoreg:1=>mem ALUcrt : add, sub, orReqWr : write dest. Reg.

33. 240-334 By Wannarat Control Signals

34. 240-334 By Wannarat Step 5 : Logic for each control signal

35. 240-334 By Wannarat Example : Load Flow

36. 240-334 By Wannarat Abstract View of implementation

37. 240-334 By Wannarat Next on Lecture 5