1. Figure 10.1 Cross-NOR S-R flip-flop: (a) Set condition; (b) Reset condition.

3. Figure 10.2 Cross-NAND S-R flip-flop.

5. Figure 10.3 Symbols for an S-R flip-flop.

6. Figure 10.4 S-R flip-flop connections using a 7402 TTL IC.

7. Example 10.1

8. Figure 10.8 Gated S-R flip-flop.

9. Figure 10.9 Function table and symbol for the gated S-R flip-flop of Figure 10–8.

10. Figure 10.7 S-R flip-flop used as a storage register.

11. Example 10.2

12. Example 10.3

13. Figure 10.12 Gated D flip-flop.

14. Example 10.4

15. Figure 10.14 The 7475 quad bistable D latch: (a) logic symbol; (b) pin configuration.

17. Example 10.5

18. Figure 10.20 The 7474 dual D flip-flop: (a) logic symbol; (b) pin configuration.

19. Figure 10.21 Positive edge-detection circuit and waveforms.