1. Saverio MINUTOLIElectronics WG - 09 June 20091 AFEC cross-talk Plots illustrating Cross-talk effect AFEC pcb investigation

2. Saverio MINUTOLIElectronics WG - 09 June 20092 During cosmics tests in Genoa, cross-talk effect has been observed. The effect is observed like blobs of hits outside the fired region of the chamber. The detector system is realized with a sandwich of three chambers, 2 CSCs type 1P and 1 CSC type 1G. Some plots will be illustrated concerning the 1P type chamber positioned in the middle of the sandwich. The plots are obtained from high-statistics (~117k events) cosmics run. CSCs set-up

3. Saverio MINUTOLIElectronics WG - 09 June 20093 2D diagrams Each wire cluster fitting a cosmics track in the telescope, all wire hits recorded are plotted as a function of the cluster center. There are two "blobs" out of the diagonal. log(z) version of the first Wire cluster Wire

4. Saverio MINUTOLIElectronics WG - 09 June 20094 Zoom around the largest blob. 2D diagrams 68.571.5

5. Saverio MINUTOLIElectronics WG - 09 June 20095 1D plots A couple of 1D plots of y-projections in the region of the blob, among those with the highest level of cross-talk. ? ?

6. Saverio MINUTOLIElectronics WG - 09 June 20096 Anode FE Card block diagram 10k 2.7pF 10k 1nF Aggressors Victims Definitions: Aggressor  signal after HV capacitor. Victim  VFAT input.

7. Saverio MINUTOLIElectronics WG - 09 June 20097 AFEC 1P type layout 4 layers: Top  VFAT fan-out and shield. INT1  Signal routing. INT2  Signal routing Bottom  Shield. 1323364659697127

8. Saverio MINUTOLIElectronics WG - 09 June 20098 Top plus INT1 65 72 85 Diagram blob

9. Saverio MINUTOLIElectronics WG - 09 June 20099 Top plus INT1, blob layout zoom 7269 8589 69 aggressor  85 victim 72 aggressor  85 victim  89 victim Exists correlation with the diagrams shown before.

10. Saverio MINUTOLIElectronics WG - 09 June 200910  Only one out of several AFEC layout points analyzed have been presented.  The correlation between the cross-talk observed from the data acquired and the layout routing is demonstrated.  The “blobs” aren’t big, they involve 3-4 channels max.  They are distributed along the AFEC pcb  10% of events could have a ghost active channel.  Phenomena observed also between internal layers INT2 and INT3 where the shield plane is absent.  Data taking in progress for the 1G-type.  Preliminary AFEC PCBs check have evidenced that each pcb type have some critical points (possible “blobs”). Conclusions

11. Saverio MINUTOLIElectronics WG - 09 June 200911  Increase the AFEC pcb stack-up from 4 to 6 layers.  This modification insert two extra ground shield planes between Top  INT1, and INT1  INT2.  This structure, signal planes interleaved with gnd planes have been adopted for the CFEC layout design with excellent results. –Confirmed also by the AFEC itself, in the areas where the traces are well shielded.  Starting now with the production, we will get the new PCBs ready to be mounted on the CSCs at end of July.  Material procurement in progress. –HV capacitors –Panasonic connectors available.  Off line analysis –Aggressor  Victim is always unidirectional  possible mask table. Solution(s)