1. jump (op-code= 20) unconditional jump Forms allowed by the assembler: jump [ra + constant] jump [ra + variable] jump [ra + address] jump [ra + label] For all the above instructions: (ra=0):PC← PC+(8αC2 )©C2, (ra≠0):PC← R[ra]+(8αC2 )©C2 ;* * C2 is computed by sign extending the constant, variable, address, or (label –PC) Type II  uses different forms as allowed by a particular assembler Op-codera 0 8 10 11 15 c2 7 Recall from pervious lecture

2. CS501 Advanced Computer Architecture Lecture14 Dr.Noor Muhammad Sheikh

3. Review

4. jump (op-code= 20) unconditional jump Forms allowed by the assembler: jump [ra + constant] jump [ra + variable] jump [ra + address] jump [ra + label] For all the above instructions: (ra=0):PC← PC+(8αC2 )©C2, (ra≠0):PC← R[ra]+(8αC2 )©C2 ; C2 is computed by sign extending the constant, variable, address, or (label –PC) Type II  uses different forms as allowed by the assembler Op-codera 0 8 10 11 15 c2 7 1. Constant, Variable, address or (label – PC) should be in the range -128 to + 127 2. IF jump [r0+a] is used, it means jump [a] 3. jump [-r2] is not allowed by the assembler 4. Target address should always be EVEN Types of unconditional jumps possible: Direct Indirect PC relative (near) Register relative (far) Recall from pervious lecture

5. Structural RTL for the jump instruction Format: jump [ra+c2] StepRTN T0-T2Instruction Fetch T3(ra=0): A← PC, (ra≠0): A ← R[ra]; T4C ← A + c2(sign extend); T5PC ← C; Unconditional jump

6. StepRTL T0-T2Instruction fetch T3n ← IR ; T4C ← (Nα0) © R[rb] ; T5R[ra] ← C; Structural RTL for the shiftr instruction other instructions that will have similar tables are: shiftl, asr Format: shiftr ra, rb, c1 Remember: C1 is the count field, i.e., C1 := IR

7. StepRTL T0-T2Instruction fetch T3C ← R[rb]; T4R[ra] ← C; Structural RTL for the mov instruction Format: mov ra, rb

8. StepRTL T0-T2Instruction fetch T3C ← (8αC2 ) © C2 ; T4R[ra] ← C; Structural RTL for the movi instruction Format: movi ra, c2

9. StepRTL T0-T2Instruction fetch T3C ← IO[c2]; T4R[ra] ← C Structural RTL for the in instruction Format: in ra, c2

10. StepRTL T0-T2Instruction fetch T3C ← R[ra]; T4IO[c2] ← C Structural RTL for the out instruction Format: out ra, c2

11. StepRTN T0-T2Instruction Fetch T3C ← PC; T4R[ra] ← C; T5C ← R[rb]; T6PC ← C; Structural RTL for the call instruction Format: call ra, rb

12. StepRTN T0-T2Instruction Fetch T3C ← R[ra]; T4PC ← C; Structural RTL for the ret instruction Format: ret ra

13. To external CPU bus General purpose registers (16-bits each) ALSU CH A 15 0 R0 R7 PC IR 15 0 16 lines A Unibus Data Path Implementation for FALCON-A MAR MBR … ADD SUB SHIFTL Other ALSU functions Internal processor bus R1 C Holds mul and div results AH holds MSB of dividend Recall from previous lectures

14. StepRTLControl Signals T0MAR PC, C PC + 2;PCout, LMAR, INC2, LC T1MBR M[MAR], PC C;LMBR, MRead, MARout, Cout, LPC T2IR MBR;MBRout, LIR T3Instruction Execution Control Signals for the Fetch operation Notes: The ALSU is assumed to include an INC2 function The memory is assumed to be fast enough to respond during a given time slot; if that is not true, wait states have to be inserted Control signals during each time slot are activated simultaneously Control signals for successive time slots are activated in sequence If a particular control signal is not shown, its value is zero

15. External FALCON-A CPU interface FALCON-A CPU FOUR Control bus signals: MRead MWrite IORead IOWrite 16-bit data bus 16-bit address bus

16. External CPU Bus Activity Example problem: (a) What will be the logic levels on the external FALCON-A buses when each of the following FALCON-A instruction is executing on the processor? Complete the table given. All numbers are in the decimal number system, unless noted otherwise. (b) Specify memory addressing modes for each of the FALCON-A instructions given. Instruction Instruction RTL equivalent Address Bus <15..0> Data Bus <15..0>MReadMWrite load r7, [12+r5] addi r2, r4, 31 jump [52] store r1,[ r3+17] sub r5, r7, r6 shiftr r2, r6, 4 mov r3, r2 jz r4, [-32]

17. All memory content is aligned properly.  In other words, all the memory accesses start at addresses divisible by 2. Value in the PC = C348h Assumptions:

18. Memory Map with assumed values ……………. ….. C340h51h C341hCAh C343hD5h C344hE2h ………………… 1240h07h 1241h85h 1242hE5h 1243h3Dh Memory Address Memory Content 0020hD2h 0021h96h 0022h49h 0023h2Fh ………………… C300h44h C301h23h C302hE3h C303hD5h

19. Register Map with assumed values Register Name Content R[0]A54Bh R[1]4CB8h R[2]492Fh R[3]C2EFh R[4]2301h R[5]1234h R[6]0020h R[7]2D7Fh

20. Solution Part (a): SRC Instruction RTL equivalent Address Bus* <15..0> Data Bus <15..0> MRMRMRMR MWMWMWMW load r7, [r5+12] R[7] M[12+R[5]]1240h0785h10 addi r2, r4, 31 R[2] R[4]+31Unknown?????? jump [52] PC PC +52Unknown?????? store r1, [r3+17] M[R[3]+17] R[1]C300h4423h01 sub r5, r7, r6 R[5] R[7]-R[6]Unknown?????? shiftr r2, r6, 4 R[2] (4α0)©R[6] Unknown?????? mov r3, r2 R[3] R[2]Unknown?????? jz r4, [-32] R[4]=0:PC PC-32Unknown?????? * FALCON-A uses big-endian convention

21. Solution part (b): FALCON-A Instruction Addressing Mode load r7, [r5+12] addi r2, r4, 31 jump [52] store r1, [r3+17] sub r5, r7, r6 shiftr r2, r6, 4 mov r3, r2 jz r4, [-32] Displacement Immediate Relative Displacement Register Relative * Relative addressing is always PC relative in the FALCON-A *** Displacement addressing mode is the same as Based or Indexed. It is also the same as Register Relative addressing mode.