1. A High-Speed & High-Capacity Single-Chip Copper Crossbar John Damiano, Bruce Duewer, Alan Glaser, Toby Schaffer, John Wilson, and Paul Franzon North Carolina State University Crossbars consist of numerous input and output lines and, upon programming, can provide for the arbitrary and simultaneous connection of any input to any output. The crossbar is an essential part of many circuits requiring multi- channel signal switching, such as ATM switches, specialized VLIW video signal processors, and many DSPs. Why a Crossbar for the Copper Challenge? The need for high-speed switching technology is growing as designs grow faster, especially with the advent of SOC technology. Crossbar circuits inherently contain long, heavily-loaded interconnects and are therefore representative of a family of designs, such as SRAM, DRAM, and logic cache memory. The crossbar is simple and efficient enough to directly demonstrate the advantages offered by advanced interconnect The crossbar circuit demonstrates that the use of copper interconnect provides strong performance enhancements in a state-of-the-art circuit, while design trade-offs make copper technology attractive for embedded applications. Speed and latency are improved through the use of copper interconnect. We have also demonstrated that copper interconnect can allow for the use of a smaller crossbar cell, offering higher performance with a substantially smaller die size. Features such as high performance and smaller die size make copper technology particularly attractive for future design solutions. Cell Design Interconnect Strategy Full Report available on the web at http://www4.ncsu.edu/~jdamian/copper.html Features of the Copper Crossbar Efficient programming - fully programmable using input / write enable lines, programming performed column-by-column. It should be noted that this crossbar design is non-blocking, i.e. any input can be sent to any output, and the crossbar can operate in broadcast mode. Reset - instantly writes a "0" to all cells & clears all outputs. All output lines remain low until programmed. Reset is performed prior to re- programming or pre-configuration. Pre-configure - allows instant programming for any of several common I/O configurations within a single write cycle (<3ns). Our circuit features two built-in configurations: corner turn and broadcast mode (illustrated at right). Pre-configured input/ output mappings improve testability and can be modified to fit the needs of a specific application. Pre-Configurations CopperAluminum Simulation Results The crossbar cell is designed around a latch used to store a memory bit, as shown at left. An I/O connection is created by writing a '1' to a single memory bit within each output column. Each memory bit is written by holding the selected input 'high' while strobing the chosen output line's write_enable line, as shown at right. The stored memory bit is used as one input to a 2- input AND gate and therefore determines which input is passed to the output line. A The copper crossbar (left) functions for a square-wave input signals with f=2.67GHz while the aluminum crossbar (right) functions up to f=2.0GHz. Use of copper interconnect improved the maximum data rate more than 30%, from 4.0Gb/s to 5.33Gb/s. Total delay through the the copper crossbar (left) is 370ps vs. 425ps for the aluminum crossbar (right) - a reduction of 15%. Delays through the input lines, the crossbar cell, and the OR tree were all lower using copper interconnect. Above and Below: Tracing 2.0GHz signals through the copper (left) and aluminum (right) crossbar. Signal integrity is improved for the circuit using copper interconnect, with better OR tree performance the most notable feature. These performance advantages are the result of copper interconnect’s lower capacitive load while maintaining low resistance. stored value of '0' holds the cell output ‘ low’, while a stored value of '1' passes the input to the cell output. All crossbar cell AND outputs are combined for a given output column through an OR tree, and the output of each tree constitutes a single output line. cell schematic Crossbar programming The lower resistivity and electromigration properties of copper allow for interconnect scaling (and improved performance) while maintaining a high current density in narrow lines. An added benefit exists for embedded applications. Achieving the performance benefits of copper using aluminum interconnect for an arrayed circuit would require some or all of the following: (1) use of larger drivers within the crossbar cell; (2) use of wider interconnect to ensure that reliability specs are met; (3) increasing cell size to reduce coupling capacitance between I/O lines. Modifications required to achieve equivalent performance for aluminum interconnect would increase cell size substantially. Modifying the crossbar cell to make RC equivalent to the copper cell would require increase cell (and circuit) area by 64%. Moreover, these figures do not include further changes to aluminum linewidth required to compensate for the larger cell size and subsequently longer interconnects. The impact of this advantage alone - achieving significant die size reduction while improving performance, as demonstrated by the copper crossbar - cannot be overestimated for SOC or embedded applications. This factor aligns copper process technology with the design technology of the future. Our interconnect strategy is illustrated at right - M3 and M5 layers are of particular interest. M3 pitch is as large as possible given the number of output interconnects required and the cell size Interconnect for the final gates in the OR tree are the longest and therefore present heavy loads. The single input line per cell was placed on M5 to minimize their resistance. Interdigitated ground lines shield the signal lines, reducing the likelihood of crosstalk and delay problems introduced by self-inductance. The capacitive load on M3 and M5 interconnect - the input and output stages respectively - limits the maximum input signal frequency and has the most impact on its performance, especially for the M3 lines where line capacitance dominates load capacitance. Cell size advantages