1. The Patti Board Gianluca Lamanna (INFNPisa) TEL62 workshop – Pisa – 30.1.2014

2. The PATTI board PATTIThe PATTI board is a TELL1/TEL62 daughter board –Same TDCB form factor pulserMain purpose: pulser for TDCB –128 LVDS 512 channels –128 LVDS channels per board (512 channels per TELL1/TEL62) TDCB –Same TDCB connectors –Firmware, performance and primitive production stress test. Additional features: standalone testbench –LTUL0TP –LTU interface: you don’t need any L0TP to produce triggers SOB/EOB –Production of SOB/EOB: you don’t need any «SPS» –Choke/error –Choke/error signals: test of readout perfomance Versatility: PP firmware –All the functions are controlled with PP firmware Five boards in production:Five boards in production: Birmingham, Frascati, Napoli e Perugia + spare

3. DS90LV047Very simple board: DS90LV047 translators

4. PATTI layout SAMTEC 200 pins – TEL62 connector TDC connectors LVTTL-LVDS translators I/O: -4 lemos (SOB, EOB, TRIGGER, SPARE) -LTU connector -8 LEDS -Choke/error receiver Power from Murata connectors: 3.3V and +5V,-5V PPThe logic will be done in the PP SOB,EOBIndependent SOB,EOB production Trigger and choke/error LTUInterface with LTU

5. PATTI board Tell1 connector TDCB connectors Power

6. PATTI board LTU SOB, EOB, Trigger, Spare Choke & Error LEDs

7. Why you need a PATTI? The PATTI is a pulser+”standalone” trigger processor TEL62 TDCB PATTI LTU TTCex TTC Choke/Error TELL1 /TEL6 2 Sob/eob

8. Firmware

9. Choke/error generation Inspill and outspill time Sob/eob signals to the LTU Trigger sob/eob generation

10. Pulser Customizable clock (several possibilities) to read a memory  timeslot The memory is 32bx512 –Each line is the configuration of all the channels in a timeslot An external signal can be used to trigger the reading of the memory

11. Trigger generation Several possibilities to generate the trigger: –Each pulse is a trigger –Downscaled –Random or periodic uncorrelated with the pulser –Memory –external

12. Preliminary manual

13. PATTI controller frequencyConfigure the frequency of the pulser independently for each connector

14. 512 timeslots512 timeslots available for ch. Configuration –Ex: 0x0000000F ch.#0,1,2,3 ON 0x000000F0 ch.#4,5,6,7 ON 0x0000000F ch.#0,1,2,3 ON ……….

15. maskingIndividual channel masking

16. Trigger correlated/uncorrelated with the pulsers Choke/error, programmable burst

17. Status ImplementedTestedValidated Electric tests Pulser Clock variable Trigger Sob/Eob LTU comm. Choke/error TEL62 version GUI Tdspy Manual X X X X X X X X X X X X X X X X XX (50%) (20%) (80%)

18. Conclusions PATTI TDCThe PATTI is very useful build a complete test bench in the lab, both to test TDC capabilities and primitives generation The required board are in production (for the moment we have 4 boards in Pisa and 1 board at CERN) soonFirmware validation test will be completed in the soon What you need: TEL62+TDCBLTU+TTCex LEMOTDCBTEL62+TDCB to test, LTU+TTCex (in any case PATTI can produce triggers on LEMO), TDCB cables, some lemo and…. TELL1…for the moment you need a TELL1 TEL62Version for TEL62 foreseen Manual in preparation GUIGUI for control in preparation TDSPYTDSPY control in preparation