1. meeting from Mai 10th at ETHZ ArgonTube electronics Charge amplifier or linear amplifer ? Front end module 10.5.2006 Max Hess

2. Signal pulse width & charge in one pad in function from the trace angle p = 10 mm trace d pad  s pulse width: t p = d / v drift = p / (v drift  tan  ) signal charge: Q S = Q nom  p  s = Q nom  p / sin  v drift signal current: I S = Q S / t p Pad dimensions: 10 mm x 10 mm v drift = 2 mm/  s @ E drift = 1 kV/cm LEM Gain = 100 1 MIP produces 6000 e - in LAr  Q nom = 100 fC/mm 10.5.2006 Max Hess

3. Values for simulation p = 10 mm trace d pad  s  d [mm] s [mm] t p [  s] Q S [pC] I S [nA] 0.09°600.0600.1300.0060.01200 4°4°143.0143.471.6814.34200.6 10°56.057.628.005.76206 30°17.320.08.652.00231 45°10.014.15.001.41282 60°5.711.52.851.15403 * 90°010.050.10 - 3 1.0020. 10 3 v drift * therotical: t p  0 and I S  ∞ 10.5.2006 Max Hess

4. Scheme for simulation CfCf RfRf V out V out BW 10.5.2006 Max Hess

5. Ideal charge amplifier U out = 85 V Q s (pC) | 1.00 | 1.41 | 5.76 | 14.34 | 60.01 1 pF / 100 G   = 2 ms Q s = I in t p = V out C F = (300 V / 5) 1 pF = 60 pC Gain Opamp = 5 10.5.2006 Max Hess

6. Prototype ETHZ 1 pF / 470 M   = 94  s V out = 85 V (V out without R f = 300 V) V out = 6.55 V 10.5.2006 Max Hess Q s (pC) | 1.00 | 1.41 | 5.76 | 14.34 | 60.01

7. Reduced output voltage 30 pF / 15 M   = 90  s V out = 2.8 V 10.5.2006 Max Hess Q s (pC) | 1.00 | 1.41 | 5.76 | 14.34 | 60.01

8. Shorter time constant 15 pF / 15 M   = 45  s V out = 3.0 V V out = 0.42 V 10.5.2006 Max Hess Q s (pC) | 1.00 | 1.41 | 5.76 | 14.34 | 60.01

9. Linear amplifier 1 pF / 15 M   = 3  s V out = 3.0 V t p = 300  s Q s = I in t p = (V out / R F ) t p = (3V / 15 M  ) 300  s = 60 pC 10.5.2006 Max Hess Q s (pC) | 1.00 | 1.41 | 5.76 | 14.34 | 60.01

10. Linear amplifier with bandwith limitation 2 pF / 15 M   = 6  s 10.5.2006 Max Hess V out = 3.0 V Q s (pC) | 1.00 | 1.41 | 5.76 | 14.34 | 60.01

11. Linear amplifier with bandwith limitation (detail) 2 pF / 15 M   = 6  s without BW limitation BW limitation = 500 kHz (  = 0.3  s) BW limitation  350 kHz two RC (  = 0.3  s) serial 10.5.2006 Max Hess Q s (pC) | 1.00 (short signal)

12. Wath‘s the best solution ? 10.5.2006 Max Hess physical parameters LEM (pad dimensions, gain min / max) needed signal range (signal / noise, ADC resolution) off line calculation (signal fit)

13. Block Diagram for analog path +-+- +-+- +-+- -+-+ U PRE Charge amplifier -U S +U S Shaper +-+- -+-+ offset U ADC DAQ analog input stage ADC CFCF RFRF CDCD CICI RDRD R PZ RIRI RIRI RIRI RIRI R I = 1kTwisted pair flat cable shielded first idea presented in the last meeting 10.5.2006 Max Hess

14. Front end module analog in ADC serial link: 2 wire LVDS or optical REG COUNTER MUX 16:1 1 ld 12 ADCREG ld 1 12 5 clk 40 MHz 12 4 1:16 Clk = 20 MHz sampling rate = 1 MS/s SERIALIZER DS92LV16 DAQ module DESERIALIZER DS92LV16 16 FPGA AMPL 32 channels Front end module 2 system clk 40 MHz POWER consumption  20W 2 x 24VAC 10.5.2006 Max Hess ADC121S101