1. Possible solutions for the future CHOD Mauro Raggi LNF MUV and CHOD CERN 13/07/2011 1

2. The old CHOD in 2012 The typical PM signal from a hodoscope counter was 300mV high and 30 ns long. Dynamic range up to 1V (3MIP) A time resolution better than 200 ps per counter was measured from the data during NA48 data taking. 2 planes x 64 counters per plane 128 ch total 2 A cost effective and temporary solution for the readout in 2012 is treated in: A LAV FEE based readout for the CHOD @ the synchronization run TDAQ 02/2011

3. My view of the future CHOD My personal constraints –Increase the number of slab (is a factor 2 enough?) –Reuse the present scintillator material –Possibly reduce CHOD thickness (is 2 cm enough?) –Use a low cost photodetector (Sipm) –Use the LAV FEE+TELL62 readout –Keep the total number of ch<512 using 2thr Basic design choice –Maintain 2 planes of scintillators H and V –Maintain the slab structure –Introduce a longitudinal WLS readout 3

4. Single slab design 2x1 cm 4 2 cm Appropriate length up to 1 meter Strips of 2x1cm with 2 or 4 x1mm round WLS fibers for all the length read out by 1x4mm 2 SipM on one side. The strip should be painted on all sides and glued together to form super strips according to the scaling rate on the CHOD. 1 cm Hamatsu MPPC (SipM) 1x4mm 2 cm 1 cm Inner radius slab Outer radius Middle radius slab

5. Detector Layout 5 H Plane 32x2 cm wide strips 64 mm^2 of Sipm 16x4 cm wide strips 64 mm^2 of Sipm 16x6 cm wide strips 96 mm^2 of Sipm 128 slabs per CHOD plane Total 256 slabs with 960 fibers 1.5m long 256 read out channels for the whole CHOD ~ 1.5 Km of WLS fibers 960 mm^2 of SiPM (Hamamatsu or IRST) 2.4m Each of the 256 slab are optically isolated every 2cm Reduce the rate per strip by factor ~3 in the inner part due to smaller size of the strip Increase the precision of the track positioning to order ~ 1 cm 2 in inner part The size of the readout strip can be easily increased without any intervention on the detector (just read out each 2x2cm cell can reach up to 480 readout channels ) SiPM improve light collection by a factor ~3 wrt PMT

6. Understanding the rate 6 According to this picture by Spasimir the rate on the inner slabs should not exceed 400KHz which is safe for both SiPm and TDC

7. Fibers radiation hardness Modern fibers seem to be able to stand dose up to 1Mrad Even if damaged they recover up 90% of the original LY in few minutes of no beam Dose definitions: –100rad= 6.24x10 12 MeV/Kg which means 6.24x10 9 MeV/g –1Mrad = 6.24x10 13 MeV/g Max number of particle per 1 cm of slab per year –1MHzx3600s x 24h x 180days =1.5x10 13 /6.5=2.2x10 12 cm Energy per particle per fiber: –1 MeV per cm means 0.1MeV per particle –1 fiber per cm means geometrical factor of 1/10 We will have maximum 1.6x10 10 MeV/g means ~2Krad We will have more than 2 order of magnitude safety factor 7

8. Cost of the detector material Fibers cost –Double cladding 4€ meter means 1.5Km ~ 6K€ –Single cladding 2€ meter means 1.5Km ~ 6K€ Photodetector cost –Sipm 15€ per mm 2 1K sipm ~ 15K€ Low voltage sipm cost to be estimated 8 Numbers coming from recent order of similar size by KLOE thanks to M. Martini

9. Why the LAV FEE for the CHOD CHOD dynamic range (50mV, 1V) –The CHOD dynamic range much smaller to the LAV one FEE board time resolution –Few hundred of ps time resolution is more than enough with WLS fiber readout CHOD charge measurement –A precise charge measurement is not needed for the chod –The LAV FEE can give better than ~10% resolution on charge Maximum tolerable rate –The tolerable rate for single ch of LAV readout chain can reach 500KHz limited by HPTDC performance 9

10. LAV FEE working principle Details in G. Corradi, TDAQ WG dec 2010 Produce a LVDS signal of wdt equivalent to the time the signal is over threshold Clamp the signal Amplify 3 & split Compare with thr and produce an LVDS 10

11. Online Time slewing correction Exploiting the presence of a double threshold on the LAV FEE board an online slewing correction is possible for the CHOD: Define T L = leading edge time (ns) for the Lower threshold T H = leading edge time (ns) for the Higher threshold T 0 = Time of the event (ns) extrapolated to 0 mV (slewing corrected) L THR = Lower threshold value in mV H THR = Higher threshold value in mV 11 L Thr H Thr THTH TLTL T0T0

12. Test beam 2010: LAV time resolution 4 mV threshold Offline slewing correction applied using V(t) ~ t a e -tb Only TDC used in the correction More than enough for a WLS based CHOD with 1ns time resolution! 210 ps /√[E 10 E 26 /(E 10 +E 26 )] (GeV) D. Di Filippo, P. Massarotti, T. Spadaro LAV WG dec 2010 12

13. LAV FEE charge performance Q (pC ) ToT (ns) The charge resolution is very good in a limited range that matches very well CHOD requirement (1-3 MIP range) D. Di Filippo, P. Massarotti, T. Spadaro LAV WG dec 2010 13

14. New CHOD readout chain Need 8 LAV FEE board (32ch in each) 1 TEL62 or even TELL1 4 TDC boards (SCSII connection) 1 LAV Wiener crate (9U J1 only) Each TDC will house half CHOD plane The TEL62 will house the whole CHOD 4xFEE board 1xTEL62 14

15. new CHOD readout cost estimate 15 Type of equipmentNCost/1pcs LAV FEE board (32ch in each)83 K€ TDC boards41 K€ LAV Wiener crate 9U17 K€ TEL62 or even TELL114 K€ Total~ 40 K€ Plus some cables and infrastructure

16. Conclusions A strip based CHOD design is sketched –The SIPM readout is cheap and very flexible –The cost of new material is order 20~30K€ –No estimate for sipm low voltage yet A LAV FEE + TEL62 based readout seems feasible –The cost estimate for 256ch is 40-50K€ The TEL62 based readout provide an easy way of reproducing pre-trigger algorithms 16

17. Backup slides 17

18. Connections issue The input of the LAV FEE board is made by DB37 connectors The output of the CHOD is made by LEMO-00 cable 2 possible solution: –Build a patch panel with lemo IN connectors in and DB37 out –Build custom patch cables like the one below –Use the same LAV connector 18

19. FEE LAV VME9U Vth_H and Vth_L test points and adjust trimmers CAN in, CAN out USB Remote Control Local Control Sum 1 to 16 Sums 1 to 4, 5 to 8, 9 to 12, 13 to 16 Sum 1 to 16 Sums 1 to 4, 5 to 8, 9 to 12, 13 to 16 Sum 17 to 32 Sums 17 to 20, 21 to 24, 25 to 28, 29 to 32 InputsTypeOutputsType Power connectionVME J1 32 analog signals from LAV2xDB3764 LVDS output to TDC2xSCSI2 8 analog sums of 4 blocks8xLEMO-00 2 analog sums of 16 blocks2xLEMO-00 1 CAN OPEN IN connectionRJ111 CAN open OUT connectionRJ11 19

20. The FEE analog sums on CHOD One FEE boards serves 32 channels = 1/2 plane 32 analog outputs cannot all be housed on the board: (there isn’t enough space on the front panel) sum 4 slabs analog signals sum 16 slabs (16 slabs= V2 quadrant amazing!) Output via Coax 50 , Lemo-00 20

21. L0 trigger with the CHOD The presence of all CHOD ch in a single TEL62 allows the Q1 logic to be implemented the FPGAs –Each PP FPGA counts the number of hits in a plane (64 ch) –The SL FPGA makes the coincidence horizontal & vertical The use of the analog sum, a discriminator and a logic unit allow to produce a NIM simplified version of the Q1 that can be used in scaler H1 H2 H3 H4 V1 V2 V3 V4 H1&V1 H2&V2 H3&V3 Sum H1 Sum H2 Sum H3 Sum H4 Sum V1 Sum V2 Sum V3 Sum V4 H4&V4 OR NIM Q1 discr Scalers? 21

22. Sum16 based simplified Q1 Using an additional FEE board and TDC we can: –Insert the 8 sum16 (a quadrant) as 8 additional channels in the read out (see fig below). –The Q1 logic in the PP-FPGA is now easy: CH0&CH4 or CH1&CH5 or CH2&CH6 or CH3&CH7 Where CH(i)&CH(j) means |T(ch0)-T(ch4)|<10 ns Use the higher thr in veto to establish if there is more than 1 track in the sum 22 V1 CH0 V2 CH1 V3 CH2 V4 CH3 H1 CH4 H2 CH5 H3 CH7 H4 CH6

23. Sum4 based sub-quadrant Q1 Using an additional FEE board and TDC we can: –Insert the sum4 as 32 additional channels in the read out –The Q1 logic in the PP-FPGA is now improved: Can give precise localization of track Can reduce 2 tracks contamination in Q1 23 H PlaneV Plane

24. Prototype strips 20mm x 500mm x 5 mm 4 1x1 mm groves for the fibers 24