1. Winter 2006EE384x Handout 11 EE384x: Packet Switch Architectures Handout 1: Logistics and Introduction Professor Balaji Prabhakar balaji@isl.stanford.edu Professor Nick McKeown nickm@stanford.edu

2. Winter 2006EE384x Handout 12 Outline This two course sequence is about the theory and practice of designing packet switches and Internet routers. 1. Introduction: What is a packet switch? The evolution of Internet routers, their basic architectural components, and some example architectures. 2. Part I: Output Queued Switches (Emphasis on Deterministic Analysis) OQ as the simplest and ideal architecture. Output queueing and shared-memory switches. Packet arrival processes: (  )-constrained arrivals, leaky buckets, Bernoulli arrivals, bursty arrivals, adversaries. Providing bandwidth and delay guarantees, scheduling, fairness, Fair- Queueing, Generalized Processor Sharing and Deficit Round Robin. Practical difficulties: When output queued switches are impractical. Memory bandwidth and capacity scaling. Some approaches: Emulating output queued switches. Parallel packet buffers as standalone shared memory, with design examples. Routers with a single stage of buffering and constraint sets, Parallel Shared Memory Routers, Distributed Shared Memory Routers, and Parallel Packet Switches. Output link scheduling in a Distributed Shared Memory router. Combined input and output queued (CIOQ) switches, stable marriage matchings.

3. Winter 2006EE384x Handout 13 Outline 3. Part II: Input Queued Switches (Emphasis on Probabilistic Analysis). What is an input-queued (IQ) switch? Definition of IQ switch with single FCFS queue. Switching fabrics, crossbars. Head of line blocking. The balls and bins model. Proof of Karol's 2-sqrt(2) (58%) result. Virtual output queues and crossbar schedulers. Bipartite Matchings: Maximum Sized Matchings, Maximum Weight Matchings, maximal matchings. Definitions of 100% throughput. When traffic is uniform: simple RR and random matchings. When traffic matrix is known: Birkhoff- von Neuman decomposition. When traffic is not known: heuristics. PIM, iSLIP, WFA. 4. Fundamentals (Review Sessions): Introduction to probability, Poisson process, Discrete and Continuous-time Markov chains. Basic queueing theory: M/M/1, M/G/1, Little’s result, PASTA.

4. Winter 2006EE384x Handout 14 Outline EE384y 1. Part II: Input Queued Switches (Continued). Intro to Lyapunov functions, proof that max weight matching gives 100% throughput. Some case studies: The Tiny Tera architecture. The Cisco GSR 12000. 2. Part III: Other Switch Architectures Buffered crossbars. Scaling crossbars and parallelism. Multistage switches: Clos networks, 2-stage switches (random and deterministic). 3. Part IV: Other Switch Functions Address Lookup: Exact matches, longest prefix matches, performance metrics, hardware and software solutions. Packet Classification: For firewalls, QoS, and policy-based routing; graphical description and examples of 2-D classification, examples of classifiers, theoretical and practical considerations. 4. Special topics. 5. Project presentations.

5. Winter 2006EE384x Handout 15 Some logistics Web page: http://www.stanford.edu/class/ee384x Course assistant: Denise Murphy – denise@ee.stanford.edu Packard 267; Tel: (650) 723-4731denise@ee.stanford.edu TAs: Mohsen Bayati bayati@stanford.edu Nandita Dukkipati nanditad@stanford.edunanditad@stanford.edu Grades: You need to sign up with “eeclass” on the EE384x web page.

6. Winter 2006EE384x Handout 16 More Logistics Prerequisite  EE284/CS244A and familiarity with probability. Useful  Stats 116 (or EE178, EE278) and CS161 Papers  URLs to all the papers are on the eeclass web page. Grading  (40%) 5 Problem sets  (10%) Several surprise quizzes  (20%) In-class midterm exam (February 21)  (30%) Final exam ( Thursday March 23, 3:30 - 6:30 PM ) SITN Students  Same schedule as in-class students  Fax your assignment to us: (650) 618-1938 All deadlines are hard!

7. Winter 2006EE384x Handout 17 An Introduction The class starts here! Background  What is a router?  Why do we need faster routers?  Why are they hard to build? Architectures and techniques  The evolution of router architecture.  IP address lookup.  Packet buffering.  Switching.

8. Winter 2006EE384x Handout 18 What is Routing? R3 A B C R1 R2 R4D E F R5 F R3E D Next HopDestination D

9. Winter 2006EE384x Handout 19 What is Routing? R3 A B C R1 R2 R4D E F R5 F R3E D Next HopDestination D 16 32 41 Data Options (if any) Destination Address Source Address Header ChecksumProtocolTTL Fragment Offset Flags Fragment ID Total Packet LengthT.ServiceHLenVer 20 bytes

10. Winter 2006EE384x Handout 110 What is Routing? A B C R1 R2 R3 R4D E F R5

11. Winter 2006EE384x Handout 111 Points of Presence (POPs) A B C POP1 POP3 POP2 POP4 D E F POP5 POP6 POP7 POP8

12. Winter 2006EE384x Handout 112 Where High Performance Routers are Used R10 R11 R4 R13 R9 R5 R2 R1 R6 R3 R7 R12 R16 R15 R14 R8 (2.5 Gb/s)

13. Winter 2006EE384x Handout 113 What a Router Looks Like Cisco GSR 12416Juniper M160 6ft 19” 2ft Capacity: 160Gb/s Power: 4.2kW 3ft 2.5ft 19” Capacity: 80Gb/s Power: 2.6kW

14. Winter 2006EE384x Handout 114 Basic Architectural Components of an IP Router Control Plane Datapath per-packet processing Switching Forwarding Table Routing Table Routing Protocols

15. Winter 2006EE384x Handout 115 Per-packet processing in an IP Router 1. Accept packet arriving on an incoming link. 2. Lookup packet destination address in the forwarding table, to identify outgoing port(s). 3. Manipulate packet header: e.g., decrement TTL, update header checksum. 4. Send packet to the outgoing port(s). 5. Buffer packet in the queue. 6. Transmit packet onto outgoing link.

16. Winter 2006EE384x Handout 116 Generic Router Architecture Lookup IP Address Update Header Header Processing DataHdrDataHdr ~1M prefixes Off-chip DRAM Address Table Address Table IP AddressNext Hop Queue Packet Buffer Memory Buffer Memory ~1M packets Off-chip DRAM

17. Winter 2006EE384x Handout 117 Generic Router Architecture Lookup IP Address Update Header Header Processing Address Table Address Table Lookup IP Address Update Header Header Processing Address Table Address Table Lookup IP Address Update Header Header Processing Address Table Address Table DataHdrDataHdrDataHdr Buffer Manager Buffer Memory Buffer Memory Buffer Manager Buffer Memory Buffer Memory Buffer Manager Buffer Memory Buffer Memory DataHdrDataHdrDataHdr

18. Winter 2006EE384x Handout 118 Why do we Need Faster Routers? 1. To prevent routers becoming the bottleneck in the Internet. 2. To increase POP capacity, and to reduce cost, size and power.

19. Winter 2006EE384x Handout 119 Why we Need Faster Routers 1: To prevent routers from being the bottleneck 0,1 1 10 100 1000 10000 1985199019952000 Fiber Capacity (Gbit/s) TDMDWDM Packet processing PowerLink Speed 2x / 18 months2x / 7 months Source: SPEC95Int & David Miller, Stanford.

20. Winter 2006EE384x Handout 120 POP with smaller routers Why we Need Faster Routers 2: To reduce cost, power & complexity of POPs POP with large routers  Ports: Price >$100k, Power > 400W.  It is common for 50-60% of ports to be for interconnection.

21. Winter 2006EE384x Handout 121 Why are Fast Routers Difficult to Make? 1. It’s hard to keep up with Moore’s Law:  The bottleneck is memory speed.  Memory speed is not keeping up with Moore’s Law.

22. Winter 2006EE384x Handout 122 Why are Fast Routers Difficult to Make? Speed of Commercial DRAM 1. It’s hard to keep up with Moore’s Law:  The bottleneck is memory speed.  Memory speed is not keeping up with Moore’s Law. Moore’s Law 2x / 18 months 1.1x / 18 months

23. Winter 2006EE384x Handout 123 Why are Fast Routers Difficult to Make? 1. It’s hard to keep up with Moore’s Law:  The bottleneck is memory speed.  Memory speed is not keeping up with Moore’s Law. 2. Moore’s Law is too slow:  Routers need to improve faster than Moore’s Law.

24. Winter 2006EE384x Handout 124 Router Performance Exceeds Moore’s Law Growth in capacity of commercial routers:  Capacity 1992 ~ 2Gb/s  Capacity 1995 ~ 10Gb/s  Capacity 1998 ~ 40Gb/s  Capacity 2001 ~ 160Gb/s  Capacity 2003 ~ 640Gb/s Average growth rate: 2x / 18 months.

25. Winter 2006EE384x Handout 125 Outline Background  What is a router?  Why do we need faster routers?  Why are they hard to build? Architectures and techniques  The evolution of router architecture.  IP address lookup.  Packet buffering.  Switching.

26. Winter 2006EE384x Handout 126 Route Table CPU Buffer Memory Line Interface MAC Line Interface MAC Line Interface MAC Typically <0.5Gb/s aggregate capacity First Generation Routers Shared Backplane Line Interface CPU Memory

27. Winter 2006EE384x Handout 127 Second Generation Routers Route Table CPU Line Card Buffer Memory Line Card MAC Buffer Memory Line Card MAC Buffer Memory Fwding Cache Fwding Cache Fwding Cache MAC Buffer Memory Typically <5Gb/s aggregate capacity

28. Winter 2006EE384x Handout 128 Third Generation Routers Line Card MAC Local Buffer Memory CPU Card Line Card MAC Local Buffer Memory Switched Backplane Line Interface CPU Memory Fwding Table Routing Table Fwding Table Typically <50Gb/s aggregate capacity

29. Winter 2006EE384x Handout 129 Fourth Generation Routers/Switches Optics inside a router for the first time Switch Core Linecards Optical links 100s of metres 0.3 - 10Tb/s routers in development

30. Winter 2006EE384x Handout 130 Outline Background  What is a router?  Why do we need faster routers?  Why are they hard to build? Architectures and techniques  The evolution of router architecture.  IP address lookup.  Packet buffering.  Switching.

31. Winter 2006EE384x Handout 131 Generic Router Architecture Lookup IP Address Update Header Header Processing Address Table Address Table Lookup IP Address Update Header Header Processing Address Table Address Table Lookup IP Address Update Header Header Processing Address Table Address Table Buffer Manager Buffer Memory Buffer Memory Buffer Manager Buffer Memory Buffer Memory Buffer Manager Buffer Memory Buffer Memory Lookup IP Address Address Table Address Table Lookup IP Address Address Table Address Table Lookup IP Address Address Table Address Table

32. Winter 2006EE384x Handout 132 IP Address Lookup Why it’s thought to be hard: 1.It’s not an exact match: it’s a longest prefix match. 2.The table is large: about 150,000 entries today, and growing. 3.The lookup must be fast: about 30ns for a 10Gb/s line.

33. Winter 2006EE384x Handout 133 IP Lookups find Longest Prefixes 128.9.16.0/21128.9.172.0/21 128.9.172.0/24 0 2 32 -1 128.9.0.0/16 142.12.0.0/19 65.0.0.0/8 128.9.16.14 Routing lookup: Find the longest matching prefix (aka the most specific route) among all prefixes that match the destination address.

34. Winter 2006EE384x Handout 134 IP Address Lookup Why it’s thought to be hard: 1.It’s not an exact match: it’s a longest prefix match. 2.The table is large: about 150,000 entries today, and growing. 3.The lookup must be fast: about 30ns for a 10Gb/s line.

35. Winter 2006EE384x Handout 135 Address Tables are Large Source: http://www.cidr-report.org/

36. Winter 2006EE384x Handout 136 IP Address Lookup Why it’s thought to be hard: 1.It’s not an exact match: it’s a longest prefix match. 2.The table is large: about 150,000 entries today, and growing. 3.The lookup must be fast: about 30ns for a 10Gb/s line.

37. Winter 2006EE384x Handout 137 Lookups Must be Fast 12540Gb/s2003 31.2510Gb/s2001 7.812.5Gb/s1999 1.94622Mb/s1997 40B packets (Mpkt/s) LineYear

38. Winter 2006EE384x Handout 138 Outline Background  What is a router?  Why do we need faster routers?  Why are they hard to build? Architectures and techniques  The evolution of router architecture.  IP address lookup.  Packet buffering.  Switching.

39. Winter 2006EE384x Handout 139 Generic Router Architecture Lookup IP Address Update Header Header Processing Address Table Address Table Lookup IP Address Update Header Header Processing Address Table Address Table Lookup IP Address Update Header Header Processing Address Table Address Table Queue Packet Buffer Memory Buffer Memory Queue Packet Buffer Memory Buffer Memory Queue Packet Buffer Memory Buffer Memory Buffer Manager Buffer Memory Buffer Memory Buffer Manager Buffer Memory Buffer Memory Buffer Manager Buffer Memory Buffer Memory

40. Winter 2006EE384x Handout 140 Fast Packet Buffers Example: 40Gb/s packet buffer Size = RTT*BW = 10Gb; 40 byte packets Write Rate, R 1 packet every 8 ns Read Rate, R 1 packet every 8 ns Buffer Manager Buffer Memory Use SRAM? + fast enough random access time, but - too low density to store 10Gb of data. Use SRAM? + fast enough random access time, but - too low density to store 10Gb of data. Use DRAM? + high density means we can store data, but - too slow (50ns random access time). Use DRAM? + high density means we can store data, but - too slow (50ns random access time).

41. Winter 2006EE384x Handout 141 Outline Background  What is a router?  Why do we need faster routers?  Why are they hard to build? Architectures and techniques  The evolution of router architecture.  IP address lookup.  Packet buffering.  Switching.

42. Winter 2006EE384x Handout 142 Generic Router Architecture Lookup IP Address Update Header Header Processing Address Table Address Table Lookup IP Address Update Header Header Processing Address Table Address Table Lookup IP Address Update Header Header Processing Address Table Address Table Queue Packet Buffer Memory Buffer Memory Queue Packet Buffer Memory Buffer Memory Queue Packet Buffer Memory Buffer Memory DataHdr DataHdr DataHdr 1 2 N 1 2 N N times line rate

43. Winter 2006EE384x Handout 143 Generic Router Architecture Lookup IP Address Update Header Header Processing Address Table Address Table Lookup IP Address Update Header Header Processing Address Table Address Table Lookup IP Address Update Header Header Processing Address Table Address Table Queue Packet Buffer Memory Buffer Memory Queue Packet Buffer Memory Buffer Memory Queue Packet Buffer Memory Buffer Memory DataHdr DataHdr DataHdr 1 2 N 1 2 N DataHdr DataHdr DataHdr Scheduler

44. Winter 2006EE384x Handout 144 A Router with Input Queues The best that any queueing system can achieve.

45. Winter 2006EE384x Handout 145 A Router with Input Queues Head of Line Blocking The best that any queueing system can achieve.

46. Winter 2006EE384x Handout 146 Head of Line Blocking

47. Winter 2006EE384x Handout 147 Virtual Output Queues

48. Winter 2006EE384x Handout 148 A Router with Virtual Output Queues The best that any queueing system can achieve.

49. Winter 2006EE384x Handout 149 Maximum Weight Matching A 1 (n) N N L NN (n) A 1N (n) A 11 (n) L 11 (n) 11 A N (n) A NN (n) A N1 (n) D 1 (n) D N (n) L 11 (n) L N1 (n) “Request” Graph Bipartite Match S*(n) Maximum Weight Match

50. Winter 2006EE384x Handout 150 Outline of Proof

51. Winter 2006EE384x Handout 151 There are now many ways to achieve 100% throughput…

52. Winter 2006EE384x Handout 152 The Evolution of Switching Theory: Practice: Input Queueing (IQ) Input Queueing (IQ) Input Queueing (IQ) Input Queueing (IQ) 58% [Karol, 1987] IQ + VOQ, Maximum weight matching IQ + VOQ, Maximum weight matching IQ + VOQ, Sub-maximal size matching e.g. PIM, iSLIP. IQ + VOQ, Sub-maximal size matching e.g. PIM, iSLIP. 100% [M et al., 1995] Different weight functions, incomplete information, pipelining. Different weight functions, incomplete information, pipelining. Randomized algorithms 100% [Tassiulas, 1998] 100% [Various] Various heuristics, distributed algorithms, and amounts of speedup Various heuristics, distributed algorithms, and amounts of speedup IQ + VOQ, Maximal size matching, Speedup of two. IQ + VOQ, Maximal size matching, Speedup of two. 100% [Dai & Prabhakar, 2000]

53. Winter 2006EE384x Handout 153 Current Internet Router Technology Summary  There are three potential bottlenecks:  Address lookup,  Packet buffering, and  Switching.  Techniques exist today for:  10+Tb/s Internet routers, with  40Gb/s linecards.