1. Computer Architecture Lecture 9 MIPS ALU and Data Paths Ralph Grishman Oct. 2015 NYU

2. MIPS Instruction Set We will build a processor which implements a small subset of the MIPS instruction set load word and store word R-type: add, subtract, and, or, set less than branch on equal 10/5/15Computer Architecture lecture 92

3. Two memories To make the design simpler, we will build a machine with two memories: instruction memory data memory – “Harvard architecture” Such a design is typical for controllers but not for general-purpose PC’s (Why?) It will allow us to do both instruction fetch and execution in a single (long) clock cycle 10/5/15Computer Architecture lecture 93

4. A sequential machine Conceptually, we are still designing a sequential machine: But we will design it in pieces, and then put the pieces together 10/5/15Computer Architecture lecture 94 current state next state output input

5. The pieces We need logic for instruction fetch R-type instructions load word store word branch on equal 10/5/15Computer Architecture lecture 95

6. Instruction fetch To fetch instructions in sequence, we need 10/5/15Computer Architecture lecture 96

7. Instruction fetch We will connect them up like so: 10/5/15Computer Architecture lecture 97

8. R-type instructions To implement one R-type instruction, we need our MIPS register file – set up for MIPS: two read ports, one write port, 32 32-bit registers the logic for this operation (add, sub, and, …) 10/5/15Computer Architecture lecture 98 adder

9. How do we set up a circuit which can either do ‘add’ or ‘and’ or ‘or’ … depending on some external signal? 10/5/15Computer Architecture lecture 99

10. We use a multiplexer: 10/5/15Computer Architecture lecture 910 multiplexer add and or S

11. ALU This arrangement for choosing one of the arithmetic or logical operations is termed an Arithmetic-Logic Unit, or ALU 10/5/15Computer Architecture lecture 911

12. 12 Copyright © 2014 Elsevier Inc. All rights reserved. FIGURE B.5.6 A 1-bit ALU that performs AND, OR, and addition (see Figure B.5.5). 10/5/1512Computer Architecture lecture 9

13. 13 Copyright © 2014 Elsevier Inc. All rights reserved. FIGURE B.5.8 A 1-bit ALU that performs AND, OR, and addition on a and b or a and b. By selecting (Binvert 5 1) and setting CarryIn to 1 in the least significant bit of the ALU, we get two’s comple-ment subtraction of b from a instead of addition of b to a. 10/5/1513Computer Architecture lecture 9

14. 14 Copyright © 2014 Elsevier Inc. All rights reserved. FIGURE B.5.9 A 1-bit ALU that performs AND, OR, and addition on a and b or a and b. By selecting (Ainvert 5 1) and (Binvert 5 1), we get a NOR b instead of a AND b. 10/5/1514Computer Architecture lecture 9

15. R-type instructions So we will implement the R-type instructions using our MIPS register file an ALU 10/5/15Computer Architecture lecture 915

16. Data memory To implement load word and store word, we must first add a data memory: 10/5/15Computer Architecture lecture 916

17. registers + ALU + data memory 10/5/15Computer Architecture lecture 917

18. R-type 10/5/15Computer Architecture lecture 918

19. Load word 10/5/15Computer Architecture lecture 919 from instr

20. Store word 10/5/15Computer Architecture lecture 920 from instr

21. Combining lw, sw, and R-type Note the mux-es 10/5/15Computer Architecture lecture 921

22. Branches Branch condition: register equality Branch instruction specifies offset relative to address of next instruction signed offset (branch forward / backward) offset in words 10/5/15Computer Architecture lecture 922

23. Branch logic 10/5/15Computer Architecture lecture 923

24. Full core MIPS data path 10/5/15Computer Architecture lecture 924

25. Control Logic What’s left: setting the proper control lines for each instruction We will do this in two steps ALU function for each instruction other control lines for each instruction 10/5/15Computer Architecture lecture 925

26. ALU Control Inputs ALU functionA invertBinvertOperation and or add subtract set less than nor 10/5/15Computer Architecture lecture 926

27. ALU Control Inputs ALU functionA invertBinvertOperation and0000 or0001 add0010 subtract0110 set less than0111 nor1100 10/5/15Computer Architecture lecture 927

28. ALU functions required InstructionALU function load word store word and or add subtract set less than branch on equal 10/5/15Computer Architecture lecture 928

29. ALU functions required InstructionALU function load wordadd store wordadd and or add subtract set less than branch on equalsubtract 10/5/15Computer Architecture lecture 929