Presentation is loading. Please wait.

Presentation is loading. Please wait.

Stress in Flip-Chip Solder Bumps due to Package Warpage Matt Pharr ES-240 Project 12/9/08.

Similar presentations


Presentation on theme: "Stress in Flip-Chip Solder Bumps due to Package Warpage Matt Pharr ES-240 Project 12/9/08."— Presentation transcript:

1 Stress in Flip-Chip Solder Bumps due to Package Warpage Matt Pharr ES-240 Project 12/9/08

2 Flip Chip

3 Applied Load Circuit Board e e e Si Circuit Board e e e Si W MTTF = 183 hrs MTTF = 880 hrs

4 Origin of Applied Load Si – rigid, Small CTE Solder in Molten State Substrate, large CTE Cooling

5 Finite Element Model 200 400 5000 Silicon Bismaleimide Triazene (BT) Substrate 200 150 UnderfillSolder

6 Material Properties Material Young’s Modulus, E (GPa) Poisson’s Ratio ( ) Thermal Exp. Coefficient (10 -6 /K) Sn-3.5Ag Solder50 0.323 Underfill6 0.3530 Silicon chip131 0.32.8 Bismaleimide Triazene (BT) 26 0.3915

7 Mesh  4-node linear coupled temperature- displacement quadrilateral  Fairly fine – why not?  Refined near regions of interest Edges and solder

8 Loading Conditions  Step 1: 221°C – melting point of solder  Step 2: 23°C Coupled temp-disp steady state x-Symmetry Condition on Right End  Step 3 (Attempted): 1A current through solder Coupled thermal-electric Inputted thermal properties of materials Did not converge  Not sure why

9 Loading Conditions (cont.)  Step 3: Solder and underfill at 100°C; linear variation in substrate and Si to ambient temp of 70°C Used subroutine to define this temp field  Study 2: Ran same procedure except that it was assumed that the Si was very rigid and hence could not deform in the vertical direction

10 Mises Stress  Curvature agrees with intuition  Slight variation (few MPa)

11 σ 22  Stress is ~20 MPa in Solder Bumps  Slight variation (~5 MPa)

12 Mises Stress Rigid Si  More variation in stress among solders

13 σ 22 Rigid Si  Variation in stress in solders: ~20 MPa on right-side to ~35-40 MPa near left-side

14 Discussion  Curvature seems physically intuitive  Variation in solder location seems to have minimal effect on stress Only ~5 MPa for σ 22 I guessed it would be larger but that was assuming Si is perfectly rigid  If we make Si completely rigid, we get larger variation in stress among solders

15 Lessons Learned about FEA  FEA has advantages (over experiments): Relatively easy Easy to change material parameters  Do not assume FEA can handle everything Model could be wrong Solution may not converge


Download ppt "Stress in Flip-Chip Solder Bumps due to Package Warpage Matt Pharr ES-240 Project 12/9/08."

Similar presentations


Ads by Google