1. Network Coprocessor (NETCP) Overview

2. Agenda What is NETCP? Purpose of the NETCP NETCP Block Diagram
Internet Protocol Classification Levels
Communication with the NETCP

3. NETCP Subsystem Overview
What is NETCP?
Purpose of the NETCP
NETCP Block Diagram
Internet Protocol Classification Levels
Communication with the NETCP 3

4. What is the Network Coprocessor (NETCP)?
1 to 8 up to 1.25 GHz
MSMC
MSM
SRAM
64-Bit
DDR3 EMIF
Application-Specific
Coprocessors
Power
Management
Debug & Trace
Boot ROM
Semaphore
Memory Subsystem S R I O x4 P C e x2 U A T p l i c a t o n - f / 2
Packet
DMA
Multicore Navigator
Queue
Manager h r s x3
Network Coprocessor w E G M
Accelerator
Security
PLL
EDMA
C66x™
CorePac L1
P-Cache
D-Cache
L2 Cache
HyperLink
TeraNet
Network Coprocessor consists of the following modules:
Packet Accelerator (PA)
Security Accelerator (SA)
Ethernet Subsystem
Packet DMA (PKTDMA) Controller

5. Purpose of the Network Coprocessor
Motivation behind NETCP:
Use hardware accelerators to do L2, L3, and L4 processing and encryption that was previously required to be done in software
Goals for both Packet Accelerator and Security Accelerator:
Offload DSP processing power
Improve system integration
Allow cost savings at the system level
Expand DSP usability within current products
Allow DSP usage in new product areas
Security Key applications:
IPSec tunnel endpoint (e.g. LTE eNB, ...)
Secure RTP (SRTP) between gateways
Air interface (3GPP, Wimax) security processing 5

6. NETCP Block Diagram . : 32-bit VBUSP TeraNet SCR
Config 32-bits
32-bit VBUSP TeraNet SCR
CPU/3 CFG TeraNet SCR
PKTDMA Controller
PKTDMA Controller
Pass 1 LUT
PDSP+ 1
Timer16 1
PKTDMA_VBUSM_TXRX bits
CDE
Timer16 2
Pass 1 LUT
PDSP+ 2
32-bit VBUSP TeraNet SCR
Streaming Interface Switch
Timer16 3
CPU/3 Main TeraNet SCR
CDE
Timer16 4
Pass 1 LUT
PDSP+ 3
Timer16 5
CP_ACE Security
Unit
CP_ACE Security
Unit
CDE
Timer16 6
Pass 2 LUT
PDSP+ 4
CDE
PDSP Scratchpad RAM 1
PDSP+ 5
PDSP Scratchpad RAM 2
Switch Status INTS
CDE . :
PDSP+ 6
3-Port Ethernet Switch
SGMII 0
SERDES
CPSGMII
CDE
PDSP Scratchpad RAM n
SGMII 1
SERDES
CPSGMII
CPMDIO
MDIO 0 INTS
PA Stats
INTD

7. Packet DMA in NETCP . . . FFTC (B) Queue Manager Subsystem SRIO
FFTC (A)
Queue Manager
PKTDMA 1
PKTDMA 2
PKTDMA 3 4 . 5 . .
8192
AIF
PKTDMA
Network
Coprocessor
PKTDMA
PKTDMA
NEW

8. Internet Protocol Classification Layers
Layer 2 (L2): Media Access Control (MAC) Layer
IEEE standard
Layer 3 (L3): Internet Layer
Internet Protocol Version 4 (IPv4)
Internet Protocol Version 6 (IPv6)
Custom L3 Classification
Layer 4 (L4): Transport Layer
User Datagram Protocol (UDP)
Transmission Control Protocol (TCP)
Custom L4 Classification
So now let’s give an overview of the packet classification layers supported by the packet accelerator.
The packet accelerator uses provides the ability to classify packets based on Layer 2, Layer 3, and Layer 4 packet headers.
Layer 2, the MAC layer, refers to MAC, VLAN, LLC snap headers.
Layer 3, the IP layer, refers to IP headers, such as IPv4 or IPv6.
Layer 4, the transport layer, refers to udp, tcp, or other layer 4 headers
Example Packet L2 L3 L4
Data
MAC
IPv4
UDP
Payload

9. Communication with the NETCP
NETCP relies on QMSS and PKTDMA to communicate with the CorePac.
TX Queue Mapping
Q640: PDSP1
Q641: PDSP2
Q642: PDSP3
Q643: PDSP4
Q644: PDSP5
Q645: PDSP6
Q646: SASS0
Q647: SASS1
Q648: Switch
RX Queues
Can use any general purpose queues (Q864-Q8191)
Can also use other special purpose queues (e.g )
PKTDMA TX channels mapped to QMSS PA TX queues
Lets discuss how to use the Multicore navigator to communicate with the network coprocessor.
Lets begin with transmitting data to the network coprocessor. To transmit data to the network coprocessor, queues 640 through 648 must be used. Each of these queues is mapped to a particular PKTDMA channel, and corresponds to a specific location in the NETCP.
For receive, any of the 8192 queues can be used. For communication with the host, the general purpose queues or the high or low priority accumulation queues will probably be used.
Unlike the transmit queues, the packet dma receive channels are not tied to a specific queue.

10. For More Information
For more information, refer to the Network Coprocessor (NETCP) User Guide.
For questions regarding topics covered in this training, visit the support forums at the TI E2E Community website.