1. Reduction of Register File Power Consumption Approach: Value Lifetime Characteristics - Pradnyesh Gudadhe

2. Paper being presented: Reducing Register File power Consumption by Exploiting Value Lifetime Characteristics Reducing Register File power Consumption by Exploiting Value Lifetime Characteristics –Zhigang Hu –Margaret Martonosi (Department of Electrical Engineering, Princeton university ) Source: Workshop on Complexity Effective Designs (WCED), (held in conjunction with ISCA-27), June 2000.

3. Scenario Trend towards wider instruction issue and larger instruction window Trend towards wider instruction issue and larger instruction window Size and number of Read/Write ports of register file is increasing Size and number of Read/Write ports of register file is increasing Register file consumes substantial amount of power Register file consumes substantial amount of power Register accesses show good temporal locality Register accesses show good temporal locality Register values are short lived. (30-65%) Register values are short lived. (30-65%)

4. Introduction Instruction memory Address 4 32 0 Add Add result Shift left 2 I n s t r u c t i o n IF/IDEX/MEMMEM/WB M u x 0 1 Add PC 0 Address Write data M u x 1 Registers Read data 1 Read data 2 Read register 1 Read register 2 16 Sign extend Write register Write data Read data Data memory 1 ALU result M u x ALU Zero ID/EX

5. Register file in 5-stage pipeline Has 6 ports Has 6 ports –4 input ports ( 3 – register number, 1 write data ) –2 output ports ( 2 – registers read from register file) Write register number input port and write register data port are active in write back stage Write register number input port and write register data port are active in write back stage Number of ports increases in multiples of the cores added in multicore scenario. Number of ports increases in multiples of the cores added in multicore scenario. Register file accessed more extensively in case of multicore scenario. Register file accessed more extensively in case of multicore scenario.

6. Why register file power consumption? In the Motorola M.CORE architecture, the register file consumes 16% of the total processor power and 42% of the data path power. Register file power may reach 25% of the total processor power when running embedded applications. Due to the comparatively small size of the register file, the power density (power per unit area) of the register file is very high.

7. Contribution towards the problem: Solution: Solution: Reduce the number of register file accesses. Idea: Idea: Have a “holding talk” to buffer results between Functional Units and register File. This holding tank is “Value Aging Buffer” This will reduce Register file access and hence reduce power consumption.

8. Decode: Physical Register Assigned if instruction produces value Physical register filled with data at Instruction completion (Write Back) Following instructions fetch data from Results bus or physical register Pre-Value Active Value Value kept since last use, in case of misprediction or exception Free the value when new instruction with same physical register destination is committed successfully. Save for exception

9. Value Lifetime Characteristics Pre-Value: Time period between register tag has been allocated and value produced. Pre-Value: Time period between register tag has been allocated and value produced. Active Value: Time period between value first produced and put in a register until last read or write that uses the value. Active Value: Time period between value first produced and put in a register until last read or write that uses the value. Save for Exception: Time for which value is kept since it was last used until it can be freed. Save for Exception: Time for which value is kept since it was last used until it can be freed.

10. Note: Active Value has average length of 3- 4 cycles. (Very less as compared to others.) Note: Active Value has average length of 3- 4 cycles. (Very less as compared to others.)

11. Value Aging Buffer (VAB)

12. FIFO Buffer FIFO Buffer VAB stores: VAB stores: –Physical register number –Data –Valid bit Number of entries: Number of entries: ~ 1/4 th of number of physical registers ~ 1/4 th of number of physical registers VAB postpones register file accesses VAB postpones register file accesses

13. Register read using VAB Look for register in VAB, Look for register in VAB, –If found, then fetch the value from VAB –If not found, then fetch it from register file with one cycle extra penalty. (Rare) VAB Miss Rate = No. of misses in VAB VAB Miss Rate = No. of misses in VAB Total no. of read requests Total no. of read requests

14. Register Write using VAB Value produced by functional units is added to VAB. Value produced by functional units is added to VAB. If VAB is full, then oldest VAB entry is evicted. If VAB is full, then oldest VAB entry is evicted. VAB Eviction Rate = Ratio of VAB entries VAB Eviction Rate = Ratio of VAB entries evicted to register file. evicted to register file.

15. Freeing a register using VAB When? When? –Misprediction or Exception –Another instruction with same destination register is committed. VAB entry freed by resetting the valid bit VAB entry freed by resetting the valid bit

16. Exception & Misprediction Handling Exceptions: VAB is dumped into register file Exceptions: VAB is dumped into register file –Rare: Impact on performance & power is less Misprediction: High penalty. Misprediction: High penalty. –VAB passed in the branch stack, so that VAB content can be copied quickly.

17. VAB with Location bit One extra cycle if value not found in VAB. One extra cycle if value not found in VAB. –Major source of performance loss Store 1 bit per Physical Register to indicate its location. Store 1 bit per Physical Register to indicate its location. = 1 if register is in VAB = 0 if register is in register file Map of physical register numbers and location bits, before accessing VAB or register file to make decision. Map of physical register numbers and location bits, before accessing VAB or register file to make decision.

18. Statistics 1 of 3 16 entry VAB captures 50-70% of read-requests. 16 entry VAB captures 50-70% of read-requests. Only 26-56% of all values produced need to be saved in register file Only 26-56% of all values produced need to be saved in register file

19. Statistics 2 of 3 Cons: 5% less IPC Cons: 5% less IPCBut….. Saves about 30% of register file power. Saves about 30% of register file power.

20. Statistics 3 of 3 Same performance in with and without VAB. Same performance in with and without VAB. 9% power saving. 9% power saving.

21. Impact on CSE 520 A new power reduction technique A new power reduction technique Motivation to come up with VAB design for multicore architecture. Motivation to come up with VAB design for multicore architecture. Register file is a crucial element in data path which decides cycle width. And hence, performance, IPC, throughput, power consumption; everything depends on it. Register file is a crucial element in data path which decides cycle width. And hence, performance, IPC, throughput, power consumption; everything depends on it. Key factor to improve CPU’s overall performance and efficiency Key factor to improve CPU’s overall performance and efficiency

22. Impact on the project: The project: The project: –Simulation of 5-stage pipelined datapath with Value Added Buffer Aim: Aim: –Simulation of 5-stage pipeline –Integrating VAB in the 5-stage pipeline simulation –Performance measurement of simulated processor with and without VAB. –Exploring further improvement tactics

23. Project Details:

24. Opportunities in the project: Exact, strategic placement of VAB in datapath Exact, strategic placement of VAB in datapath Possibilities of reducing register file ports Possibilities of reducing register file ports Analysis of register file accesses data Analysis of register file accesses data Impact of VAB on performance Impact of VAB on performance Experience of actually implementing theory proposed by the paper may highlight some cons of the concept. Experience of actually implementing theory proposed by the paper may highlight some cons of the concept. Validating proposed theory Validating proposed theory Verifying functionalities of VAB Verifying functionalities of VAB

25. THANK YOU! THANK YOU! Questions?