1. Advanced Pixel Architectures for Scientific Image Sensors Rebecca Coath, Jamie Crooks, Adam Godbeer, Matthew Wilson, Renato Turchetta CMOS Sensor Design Group and the SPiDeR Collaboration Rutherford Appleton Laboratory, STFC 1

2. Introduction The INMAPS Process High Resistivity Epitaxial Layers 4T Pixels Designs utilising these technologies – FORTIS Basic test results Charge collection efficiency scan results Radiation hardness testing results Beam test results – TPAC Update on progress Summary 2

3. The INMAPS Process Additional pn junctions within a pixel can reduce the charge collected by the diode By omitting PMOS transistors, the capability of the readout circuitry is reduced The ideal situation is to achieve full CMOS capability and maximise the charge collection efficiency 3

4. The INMAPS Process A special deep P-well layer was developed to overcome this problem The deep P-well protects charge generated in the epitaxial layer from being collected by parasitic pn junctions By adding deep P-well underneath the readout circuitry, the charge collection efficiency is maximised and full CMOS capability within a pixel is achievable 4

5. ) High Resistivity Epitaxial Layers A high resistivity epitaxial layer should improve charge collection efficiency, cross talk effects and radiation hardness by allowing the depletion region of the diode to extend further into the silicon Epitaxial thickness: up to 18µm Typical resistivity ~ 10-100Ωcm High resistivity ~ 1-10kΩcm Green = Nwell diode Blue = P-type epitaxial layer 5

6. 3T Versus 4T Pixels 3T CMOS Simple architecture Readout and charge collection area are the same 4T CMOS Three additional elements Readout and charge collection area are at different points 6

7. 4T Pixel Advantages e- q = CV => V = q/C V = q/C small V = q/C large 7 Low Noise – In a 4T pixel, the readout node is separated from the charge collection area – The reset noise, as well as some fixed pattern noise (FPN) can therefore be removed by in-pixel correlated double sampling (CDS) High Conversion Gain – Charge is collected on the diode then transferred via TX to the floating diffusion node (FD) – The smaller the capacitance, the higher the conversion gain – By minimising the size of the floating diffusion node, the capacitance can be minimised to give a high conversion gain

8. The Sensors FORTIS (4T Test Image Sensor) – 2 versions (FORTIS 1.0 and FORTIS 1.1) – 13 different variants on a 4T pixel architecture – FORTIS 1.1 contains an optimised process for low noise and was fabricated on a high resistivity epitaxial layer and with deep P-well TPAC (Tera-Pixel Active Calorimeter) – Presented last year at TWEPP ’08 (Naxos, Greece) – In-pixel circuitry due to use of deep P-well led to ~160 transistors per pixel – Latest version was also fabricated on a high resistivity epitaxial layer Both use 0.18µm INMAPS process 8

9. FORTIS 1.0 FORTIS – “4T Test Image Sensor” Consists of: – Simple readout architecture (row/column address logic, analogue output circuitry) – Twelve different pixel variants Original Designs Variations in source follower size Variations in diode size Variations in pixel size 9

10. Results Conversion gain at output: 61.4μV/e- Noise: 5.8e- Linear full well capacity: 19000e- Estimated MIP S/N ratio: 166 10

11. FORTIS 1.1 The decoder logic, pad ring, analogue output circuitry, biases and other external periphery were left untouched for FORTIS 1.1 Seven processing variations, including deep P-well and high resistivity epitaxial layers Optimised process to reduce noise distribution and increase overall gain 11

12. Test Results ParameterStandardDPWHigh Res FORTIS 1.0 Noise (e-)8.78.47.611.3 Gain ( µV/e-) 52.556.855.938.2 Gain at FD ( µV/e-) 58.363.162.147.7 Linear Full Well Capacity (e-) 32200308003110024400 Estimated MIP S/N Ratio 11011412685 12

13. Charge Collection Efficiency Scans A white light source focused to a 2.2µm spot size was used to horizontally scan across three adjacent pixels to determine the charge collection efficiency of FORTIS Two chips were compared – Standard epitaxial layer – High resistivity epitaxial layer The results show the benefits of using a high resistivity epitaxial layer 13

14. Charge Collection Efficiency Scans Standard Resistivity Epitaxial Layer Diode Metal on pixel 14 0 10 20 30 40 50 60 70 80 90 5x10 4 4x10 4 3x10 4 2x10 4 1x10 4 0x10 4 Crosstalk between pixels (15µm pitch) Horizontal Distance (µm) ADC Count (DN)

15. Charge Collection Efficiency Scans High Resistivity Epitaxial Layer Diode Metal on pixel 15 0 10 20 30 40 50 60 70 80 90 Crosstalk reduced due to increase in depletion region of diode and reduction in charge diffusion 5x10 4 4x10 4 3x10 4 2x10 4 1x10 4 0x10 4 Horizontal Distance (µm) ADC Count (DN)

16. Radiation Hardness Testing FORTIS 1.0 has undergone radiation hardness testing with 50kV x-rays The chips have been irradiated in steps up to 1MRad (so far!) and are retested after each step – Chip is still functional up to 500kRad – At 1MRad, chips begin to show signs of damage In-between irradiations, the chips are stored at a temperature of ~-25°C to reduce the effects of annealing 16

17. Results 17

18. Beam Test Results As part of the SPiDeR (Silicon Pixel Detector R&D) collaboration, FORTIS 1.0 and FORTIS 1.1 have just returned from a beam test at CERN Chips on standard epitaxial layers, high resistivity epitaxial layers and with deep P-well were taken They were tested with 120GeV pions The results are currently being analysed… The above plot shows the first detection of MIPs with a 4T architecture! 18

19. TPAC TPAC (Tera-Pixel Active Calorimeter) was presented at TWEPP last year Monolithic Active Pixel Sensor for a “Tera-Pixel” ECAL at the ILC Each of the ~28,000 pixels contains sophisticated circuitry which would not be possible without INMAPS TPAC was the first of our designs to be manufactured with deep P-well, and was also manufactured on high resistivity epitaxial layers 19 In each pixel:

20. TPAC TPAC also went to the beam test at CERN as part of SPiDeR: – 6 TPAC sensors (layers) in stack – 170,000 pixels in total – 1cm x 1cm active area – Three scintillators/PMTs installed – Used to tag time of particles within bunch trains Early indications show that the data obtained is good – Scintillators/PMTs give good time tags for particles – Events were seen in all layers (including high resistivity) USB-based DAQ setup on H6B beam line at CERN X-X correlation plot for two layers (back-to-back) 20

21. Summary FORTIS (4T Test Image Sensor) – 4T pixels – Low noise (5.8e-) and high sensitivity to small amounts of charge – Tested for radiation hardness up to 1MRad Rad-hard up to ~500kRad – FORTIS 1.1 will undergo radiation hardness testing TPAC (Tera-Pixel Active Calorimeter) – First chip to successfully use deep P-well implant – TPAC will be taken to DESY beam test in early 2010 to be tested with 1-6GeV electrons Both sensors have been manufactured with the INMAPS 0.18µm process, with and without deep P-well and on both standard and high resistivity epitaxial layers Both sensors and the processing variations are currently being evaluated for use in a digital electromagnetic calorimeter (DECAL) design and for scaling up to a 5cm x 5cm active area – UK funded project, SPiDeR – SPiDeR also works on MAPS for vertex detection and tracking 21

22. Acknowledgements Thanks to the SPiDeR collaboration: – B. Allbrooke, O. Miller, N.K. Watson, J.A. Wilson School of Physics and Astronomy, University of Birmingham – D. Cussans, J. Goldstein, R. Head, S. Nash, J.J. Velthuis University of Bristol – P.D. Dauncey Blackett Laboratory, Imperial College London – R. Gao, Y. Li, A. Nomerotski University of Oxford – R.E. Coath, J.P. Crooks, R. Turchetta CMOS Sensor Design Group, Technology Department, STFC Rutherford Appleton Laboratory – C.J.S. Damerell, M. Stanitzki, J. Strube, M. Tyndel, S.D. Worm, Z. Zhang Particle Physics Department, STFC Rutherford Appleton Laboratory Thanks also to Adam Godbeer, Carl Morris, Daniel Packham, Tim Pickering and Matthew Wilson for their contributions 22