Darmstadt University of Technology- 1 - Sequential Verification by Symbolic Simulation Darmstadt University of Technology Dept. of Electrical and Computer.

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Darmstadt University of Technology- 1 - Sequential Verification by Symbolic Simulation Darmstadt University of Technology Dept. of Electrical and Computer Engineering Germany Gerd Ritter

Darmstadt University of Technology- 4 - r r+1; if m = 0 thenr r+1; else r 000; r[2] clk & r[1] & r[0] & r & & clk ctrl m

Darmstadt University of Technology- 5 - Verification Scope automatic interpreted sequential Verification no significant user interaction no insight into the verification process automatic

Darmstadt University of Technology- 6 - Verification Scope automatic interpreted sequential Verification demonstrating the verification goal requires an interpretation of functions not necessary for some problems where specialized approaches perform better

Darmstadt University of Technology- 7 - Verification Scope automatic interpreted sequential Verification not only logic verification several control steps/cycles to demonstrate verification goal è different numbers of steps in specification and implementation

Darmstadt University of Technology- 8 - Outline introduction essentials of our symbolic simulation approach example of gate-level verification experimental results application areas & conclusion

Darmstadt University of Technology- 9 - techniques denoted symbolic simulation or symbolic evaluation developed since the 1970s the following four essentials è distinguish our symbolic simulation approach è permit sequential verification at different levels of abstraction Essentials

Darmstadt University of Technology- 10 - terms are never manipulated, e.g., by canonizing or rewriting them 1. Essential a b = a (b c) b a Suppose = 0c

Darmstadt University of Technology- 11 - terms are never manipulated, e.g., by canonizing or rewriting them 1. Essential relationships are notified at equivalence classes instead a c 0 a (b c)b a a (b c) b

Darmstadt University of Technology- 12 - ac+e+x[6:15]+y; 2. Essential ac+e+x[6:15]+y+ac+e+x[6:15]+y; Problem:term-size explosion possible if rewriting register with expression assigned to it ac ac+e; bc x[6:15]+y; if ir=000111 then ac ac + bc ; res ac + ac ; else...

Darmstadt University of Technology- 13 - ac ac+e; bc x[6:15]+y; if ir=000111 then ac ac + bc ; res ac + ac ; else... 2. Essential ac 1 ac+e; bc 1 x[6:15]+y; if ir=000111 then ac 2 ac 1 + bc 1 ; res 1 ac 2 + ac 2 ; else... Problem:term-size explosion possible if rewriting register with expression assigned to it Solution:several register assignments along a valid path are explicitly distinguished

Darmstadt University of Technology- 14 - ac ac+e; bc x[6:15]+y; if ir=000111 then ac ac + bc ; res ac + ac ; else... 2. Essential ac 1 ac+e ac 1 ac+e; bc 1 x[6:15]+y; if ir=000111 then ac 2 ac 1 + bc 1 ; res 1 ac 2 + ac 2 ; else... ac ac 2 ac 1 +bc 1 Problem:term-size explosion possible if rewriting register with expression assigned to it Solution:several register assignments along a valid path are explicitly distinguished

Darmstadt University of Technology- 15 - the verfication problem is not reduced to a single formula which is checked afterwards 3. Essential Verification Problem Formula checker if z=101 then a¬ b d elsif a¬ b d then if(a+b)<(c+e)........ TRUE or FALSE

Darmstadt University of Technology- 16 - 3)a b the verfication problem is not reduced to a single formula which is checked afterwards simulation is guided along valid, i.e., logical consistent paths instead 3. Essential... if a = b then c y+5; else c a; if a = c then res...; else res...; 3 valid paths 1)a = b =c 2)a = b c

Darmstadt University of Technology- 17 - equivalence of subterms is sufficient in most cases to reveal equivalences of terms 4. Essential a a (b c)b a a (b c) b c 0

Darmstadt University of Technology- 18 - Challenges equivalence detection of symbolic terms consistent case splits during simulation è must consider sequential behaviour è avoid false paths

Darmstadt University of Technology- 19 - Equivalence detection flexible use of an open library of different equivalence detection techniques during symbolic simulation on the fly è good compromise between accuracy and speed è not focus of this talk decision diagram based techniques reveal special equivalences which occur seldom or are hard to detect Make the common case fast

Darmstadt University of Technology- 20 - r r+1; if m = 0 thenr r+1; else r 000; r[2] clk & r[1] & r[0] & r & & clk ctrl m

Darmstadt University of Technology- 23 - è duplicate according to number of cycles (here: 2 cycles) Gate-level design describes only one cycle... r[2] clk & r[1] & r[0] & r & & clk ctrl m

Darmstadt University of Technology- 24 - r[2] clk & r[1] & r[0] & r & & clk ctrl m Break feed-back of registers... r[2] clk & r[1] & r[0] & r & & clk ctrl m

Darmstadt University of Technology- 25 - r[2] clk & r[1] & r[0] & r & & clk ctrl m r[2] clk & r[1] & r[0] & r & & clk ctrl m r[2] r[1] r[0] Register-outputs of previous cycle are inputs of next cycle ctrl

Darmstadt University of Technology- 26 - r[2] clk & r[1] & r[0] & r & & clk ctrl m r[2] clk & r[1] & r[0] & r & & clk ctrl m r[2] r[1] r[0] cycle 1cycle 2 initial symbolic values final symbolic values ctrl

Darmstadt University of Technology- 27 - Assumption about initialization of ctrl -register r[2] clk & r[1] & r[0] & r & & clk ctrl m1m1 r[2] clk & r[1] & r[0] & r & & clk ctrl m r[2] r[1] r[0] ctrl

Darmstadt University of Technology- 28 - r[2] clk & r[1] & r[0] & r & & clk ctrl m1m1 r[2] clk & r[1] & r[0] & r & & clk ctrl m r[2] r[1] r[0] 0 ctrl clk ctrl Assumption about initialization of ctrl -register

Darmstadt University of Technology- 29 - Indexing the different register values r[2] clk & r[1] & r[0] & r & & clk ctrl m1m1 r[2] clk & r[1] & r[0] & r & & clk ctrl m r[2] r[1] r[0] ctrl 0 clk ctrl

Darmstadt University of Technology- 30 - r 2 [2] clk & r 2 [1] & r 2 [0] & r & & clk ctrl m1m1 r 1 [2] clk & r 1 [1] & r 1 [0] & r & & clk ctrl m r[2] r[1] r[0] ctrl 2 ctrl 3 0 clk ctrl ctrl 1 Indexing the different register values

Darmstadt University of Technology- 31 - 1ctrl 1 nand m r 2 [2] clk & r 2 [1] & r 2 [0] & r & & clk ctrl m1m1 r 1 [2] clk r 1 [1] r 1 [0] r & clk ctrl m r[2] r[1] r[0] ctrl 2 ctrl 3 0 ctrl 1 0 0 1 clk ctrl & & & &

Darmstadt University of Technology- 32 - (not r[0])r 1 [0] (ctrl 1 nand m) and (not r[0]) r 2 [2] clk & r 2 [1] & r 2 [0] & r & & clk ctrl m1m1 r 1 [2] r 1 [1] r 1 [0] & clk ctrl m r[2] r[1] r[0] ctrl 2 ctrl 3 0 ctrl 1 & clk ctrl r clk 1 & & &

Darmstadt University of Technology- 33 - (r[1] xor r[0])r 1 [1] (ctrl 1 nand m) and (r[1] xor r[0]) r 2 [2] clk & r 2 [1] & r 2 [0] & r & & clk ctrl m1m1 r 1 [2] r 1 [1] r 1 [0] & & clk ctrl m r[2] r[1] r[0] ctrl 2 ctrl 3 0 clk ctrl ctrl 1 r clk 1 & & &

Darmstadt University of Technology- 34 - r 2 [2] clk & r 2 [1] & r 2 [0] & r & & clk ctrl m1m1 r 1 [2] clk & r 1 [1] & r 1 [0] & r & & clk ctrl m r[2] r[1] r[0] ctrl 2 ctrl 3 0 clk ctrl ctrl 1

Darmstadt University of Technology- 36 - r1r1 r+1 s r 2 [2] clk & r 2 [1] & r 2 [0] & r & & clk ctrl m1m1 r 1 [2] clk & r 1 [1] & r 1 [0] & r & & clk ctrl m r[2] r[1] r[0] ctrl 2 ctrl 3 0 clk ctrl ctrl 1 ?

Darmstadt University of Technology- 37 - Decision Diagram based Techniques reveal special equivalences which occur seldom or are hard to detect build formula for equivalence è use results of other equivalence detection techniques on the fly è information notified at equivalence classes check formula by vectors of OBDDs

Darmstadt University of Technology- 38 - Formula checked in this example r+1 r 1 [2] clk & r 1 [1] & r 1 [0] & r & & m r[2] r[1] r[0] 0 clk ctrl

Darmstadt University of Technology- 39 - Formula checked in this example a+1 & a[2] a[1] a[0]

Darmstadt University of Technology- 40 - ? r1r1 r+1 s r 2 [2] clk & r 2 [1] & r 2 [0] & r & & clk ctrl m1m1 r 1 [2] clk & r 1 [1] & r 1 [0] & r & & clk ctrl m r[2] r[1] r[0] ctrl 2 ctrl 3 0 clk ctrl ctrl 1

Darmstadt University of Technology- 41 - r 2 [2] clk r 2 [1] r 2 [0] r & clk ctrl m1m1 r 1 [2] clk & r 1 [1] & r 1 [0] & r & clk m r[2] r[1] r[0] ctrl 2 ctrl 3 0 ctrl 1 0 clk ctrl & 1 1 & & & 0 &

Darmstadt University of Technology- 42 - r 2 [2] r 2 [1] & clk ctrl m1m1 r 1 [2] clk & r 1 [1] & & r & & clk m r[2] r[1] r[0] ctrl 2 ctrl 3 0 clk ctrl ctrl 1 & r 1 [0] ctrl r 2 [0] 1 & & & r clk

Darmstadt University of Technology- 44 - r2r2 r 1 +1 ss r 2 [2] & r 2 [1] & r 2 [0] & & clk ctrl m1m1 r 1 [2] clk & r 1 [1] & r 1 [0] & r & & clk ctrl m r[2] r[1] r[0] ctrl 2 ctrl 3 0 clk ctrl ctrl 1 ? r clk &

Darmstadt University of Technology- 45 - r 2 [2] clk & r 2 [1] & r 2 [0] & r & & clk ctrl m1m1 r 1 [2] clk & r 1 [1] & r 1 [0] & r & & clk ctrl m r[2] r[1] r[0] ctrl 2 ctrl 3 0 clk ctrl ctrl 1 (r+1)+1

Darmstadt University of Technology- 46 - r 2 [2] clk & r 2 [1] & r 2 [0] & r & & clk ctrl m1m1 r 1 [2] clk & r 1 [1] & r 1 [0] & r & & clk ctrl m r[2] r[1] r[0] ctrl 2 ctrl 3 0 clk ctrl ctrl 1 the equivalent terms are used as cutpoints

Darmstadt University of Technology- 47 - r 1 r+1; if m 1 = 0 then r 2 r 1 +1; else r 2 000; s s s s r 1 r+1; if m 1 = 0 then r 2 r 1 +1; else r 2 000; s s s s r 2 [2] clk & r 2 [1] & r 2 [0] & r & & clk ctrl m1m1 ctrl 2 ctrl 3 the equivalent terms are used as cutpoints r 1 [2] r 1 [1] r 1 [0] use again information of equivalence classes to obtain simpler formula

Darmstadt University of Technology- 48 - & a[2] a[1] a[0] a+1 Reuse hashed result è no need to build OBDDs again

Darmstadt University of Technology- 49 - ? r2r2 r 1 +1 ss r 2 [2] & r 2 [1] & r 2 [0] & & clk ctrl m1m1 r 1 [2] clk & r 1 [1] & r 1 [0] & r & & clk ctrl m r[2] r[1] r[0] ctrl 2 ctrl 3 0 clk ctrl ctrl 1 clk & r

Darmstadt University of Technology- 51 - & ctrl m1m1 r 1 [2] clk & r 1 [1] & r 1 [0] & r & clk m r[2] r[1] r[0] ctrl 2 ctrl 3 0 ctrl 1 0 clk ctrl & 1 0 & & & 1 & clk r r 2 [2] r 2 [1] r 2 [0]

Darmstadt University of Technology- 52 - r[2] clk & r[1] & r[0] & r & & clk ctrl m datapath-operations are performed on separate blocks from standard libraries

Darmstadt University of Technology- 53 - clk & & & r & ctrl m INC 3 3 no decision diagrams required for symbolic simulation datapath-operations are performed on separate blocks from standard libraries use high-level operation inc

Darmstadt University of Technology- 54 - r r+1; if m = 0 thenr r+1; else r 000; r[2] clk & r[1] & r[0] & r & & clk ctrl m cycle equivalent

Darmstadt University of Technology- 55 - r[2] clk & r[1] & r[0] & r & & clk ctrl m if m = 0 thenr r+2; else r 000; NOT cycle equivalent

Darmstadt University of Technology- 56 - Experimental Results cycles dd-checks 1.7 s 5.5 s 74 s 786 s 8 10 Synthesis tool: Synopsys ® Design Compiler

Darmstadt University of Technology- 57 - Application Area equivalence checking at different levels of abstraction è behavioral rtl è structural rtl è gate-level è FMCAD00, ASIAN99, CHARME99 et al first application to property verification è register binding verification è C. Blank, Wave2000

Darmstadt University of Technology- 58 - Limitations verification of finite sequences è the maximum number of loop iterations has to be known è verification problem can be reduced for many cyclic designs with infinite loops to check of acyclic sequences examples used in experiments still not nearly so complex as commercial designs

Darmstadt University of Technology- 59 - Conclusion sequential verification of examples at different levels of abstraction flexible use of an open library of different equivalence detection techniques è good compromise between accuracy and speed good debugging support joint work with TIMA laboratory, Grenoble