1. CEC 220 Digital Circuit Design More VHDL Fri, February 27 CEC 220 Digital Circuit Design Slide 1 of 15

2. Lecture Outline Fri, February 27 CEC 220 Digital Circuit Design More VHDL Slide 2 of 15

3. More VHDL Fri, February 27 CEC 220 Digital Circuit Design To install DirectVHDL on your personal computer:  CD in your textbook => VHDL-PE\setup-roth.exe  On the ERAU network => T:\CEC220\DirectVHDL-PE\setup- roth.exe Some examples => T:\CEC220\DirectVHDL-PE\examples Slide 3 of 15

4. More VHDL Fri, February 27 CEC 220 Digital Circuit Design Some Predefined VHDL Data Types  bit‘0’ or ‘1’  booleanFALSE or TRUE  integer -(2 31 -1) to +(2 31 -1)  character any legal character; must be in single quotes (e.g., ‘m’, ‘T’, ‘3’, ‘%’, …)  and others (e.g., real, character, …) Slide 4 of 15

5. More VHDL Fri, February 27 CEC 220 Digital Circuit Design entity – The “Black Box” description  What “ports” do I have? entity my_box is port( input_1 : in bit; input_2 : in bit; output_1: out bit); end my_box; my_box input_1 input_2 output_1 name of your “box” inputs output(s) signal type Slide 5 of 15

6. More VHDL Fri, February 27 CEC 220 Digital Circuit Design architecture – what’s inside the “Black Box” architecture my_arc1 of my_box is signal sig1: bit; begin ?? <= ???; end my_arc1; Name of your architecture block assignments Internal signals my_box my_arc1 my_arc2 Name of entity Slide 6 of 15

7. More VHDL Fri, February 27 CEC 220 Digital Circuit Design Signals and constants  signal list_of_signal_names: type_name [constraint] [:=initial_value];  signal A,B,C : bit_vector(3 downto 0):=“1111”; o The three signal all get initialized with the value “1111”  signal E,F :integer range 0 to 15; o The compiler is “smart” enough to know how many bits to use to internally represent the signals!!!  constant my_const: bit := ’1’; Initialization Slide 7 of 15

8. More VHDL Fri, February 27 CEC 220 Digital Circuit Design An Example: The Full Adder entity Full_Adder is port( X, Y, Cin: in bit; Cout, Sum: out bit); end Full_Adder; architecture my_eqns of Full_Adder is begin Sum <= X xor (Y xor Cin) after 10 ns; Cout <= (X and Y) or (X and Cin) or (Y and Cin) after 10 ns; end my_eqns; Slide 8 of 15

9. Fri, February 27 CEC 220 Digital Circuit Design Test in DirectVHDL (Full_Adder.vhd)Full_Adder.vhd Slide 9 of 15

10. More VHDL Fri, February 27 CEC 220 Digital Circuit Design What if I want to build four Full Adders to make a 4- bit adder?  Can I reuse the 1-bit FullAdder “component” more than once? Adder4 V Also, include overflow (V) Slide 10 of 15

11. More VHDL Fri, February 27 CEC 220 Digital Circuit Design entity Adder4 is -- S = A+B, Co is Carry out, V is Overflow port ( A, B : in bit_vector(3 downto 0); -- Vector, 4-bits each Ci : in bit; -- Ci is carry in, S : out bit_vector(3 downto 0); -- Vector, 4-bits Co, V : out bit); -- Co is carry out & V is overflow end Adder4; architecture my_structure of Adder4 is component Full_Adder is -- A copy of the Full_Adder port ( X, Y, Ci: in bit; Co, Sum : out bit); end component; begin FA0: Full_Adder port map (A(0), B(0), Ci, C(1), S(0)); FA1: Full_Adder port map (A(1), B(1), C(1), C(2), S(1)); FA2: Full_Adder port map (A(2), B(2), C(2), C(3), S(2)); FA3: Full_Adder port map (A(3), B(3), C(3), Co, S3); S(3) <= S3; -- Can't read from output port(s) V <= (A(3) and B(3) and not S3) or (not A(3) and not B(3) and S3) after 10 ns; end my_structure; signal C: bit_vector(3 downto 1); -- Need a signal to connect full-adders signal S3: bit; Can’t write to the input port and Can’t read from the output port Can’t write to the input port and Can’t read from the output port Slide 11 of 15

12. More VHDL Fri, February 27 CEC 220 Digital Circuit Design Run the simulation in DirectVHDL (Adder_4.vhd)Adder_4.vhd Slide 12 of 15

13. More VHDL Fri, February 27 CEC 220 Digital Circuit Design Shift operations  Given A is “10010101”  A sll 2 (shift left logical – fill with zeros)  A srl 2 (shift right logical – fill with zeros)  A sla 2 (shift left arithmetic – fill with right bit)  A sra 2 (shift right arithmetic – fill with left bit)  A rol 2 (rotate left)  A ror 2 (rotate right) 1001010100 0010010101 1001010111 1110010101 1001010110 0110010101 Slide 13 of 15

14. More VHDL Fri, February 27 CEC 220 Digital Circuit Design A tri-State Buffer library IEEE; use IEEE.std_logic_1164.all; Slide 14 of 15

15. Next Lecture Fri, February 27 CEC 220 Digital Circuit Design Latches Flip-Flops Slide 15 of 15