1. 01/04/09A. Salamon – TDAQ WG - CERN1 LKr calorimeter L0 trigger V. Bonaiuto, L. Cesaroni, A. Fucci, A. Salamon, G. Salina, F. Sargeni

2. 01/04/09A. Salamon – TDAQ WG - CERN2 L0 LKr trigger L0 LKr trigger (photon veto): cluster counting with 1-2 ns time resolution Use existing hardware (NA48 and LHC) Use the NA48 analog sums (2x8 cells) and cables replacing the “old” system with a new TELL1 based system

3. 01/04/09A. Salamon – TDAQ WG - CERN3 L0 LKr trigger Use analog sums (2x8 cells) and all the cables already exist Need to design the trigger processor read-out boards 13k analog channels analog sums LKr calorimeter DAQ 864 analog channels L0 LKr trigger read-out after L0 CTP

4. 01/04/09A. Salamon – TDAQ WG - CERN4 The TELL1 board LHCb general purpose data acquisition board 5 user programmable FPGAs, large on-board DDR memories mezzanines for 4 x 1 gbit ethernet output analog mezzanine 16 x 10 bit Stratix FPGA 25k logic elem Stratix FPGA 40k logic elem digital mezzanine 12 x 16 bit parallel bus 32 bit @ 160 MHz output interface 4 x gbit ethernet

5. 01/04/09A. Salamon – TDAQ WG - CERN5 FE boards: pulse reconstr (time, position, energy) TELL1 28 boards CTP L0 LKr Trigger: architecture Need to design two mezzanines: –one FE + ADC mezzanine –one ethernet concentrator mezzanine Two 9U crates! 13248 channels for the readout  864 channels (2x8 pixel supercells) for the trigger! ADC mezz 32 supercells Concentrator boards: merging, sorting TELL1 24 ch 5 boards Ethernet mezz ethernet 1 meter 32 ch

6. 01/04/09A. Salamon – TDAQ WG - CERN6 L0 Lkr trigger: architecture Concentrator TELL1: merging, sorting 24 Front-End TELL1 Front-End TELL1: pulse reconstruction (time, position and energy) 32 analog channels (1 channel = 2x8 liquid krypton cells analog sum) 1 analog sum (supercell) = 2x8 channels 28 FE TELL1s, 5 concentrator TELL1s, 32 supercells per TELL1

7. 01/04/09A. Salamon – TDAQ WG - CERN7 Front-End ADC mezzanine At the moment we are preparing a test stand using an existing LHCb mezzanine New mezzanine later TELL1 28 boards CTP ADC mezz 32 supercells TELL1 24 ch 5 boards Ethernet mezz ethernet 32 ch

8. 01/04/09A. Salamon – TDAQ WG - CERN8 FE to concentrator link I (new receiver) Use existing gbit ethernet output mezzanine and design new ethernet receiver on the concentrator Up to 24 ethernet input on the concentrator = 8 FE TELL1 (3 gbit per TELL1) 24 ethernet connector is (mechanically) difficult but possible Pros: lower design effort, bidirectional, added FPGA processing power on the receiver, flexible (same link for trigger and readout) Cons: ethernet overhead, lower bandwidth TELL1 Concentr Ethernet mezz ethernet Front-End Eth TX TELL1 NEW!!

9. 01/04/09A. Salamon – TDAQ WG - CERN9 FE to concentrator link II (new TX) Use existing optical receiver input mezzanine on the concentrator and design new ethernet + fiber optic transmitter Cons: higher design effort, monodirectional, no added FPGA processing power on the receiver Pros: no ethernet and added latency on the trigger path, higher bandwidth TELL1 Concentr Optical mezz ethernet Front-End Eth + opt TX TELL1 NEW!!

10. 01/04/09A. Salamon – TDAQ WG - CERN10 Pulse reconstruction (FE TELL1) Peak in space Peak in time Over threshold 7 bit reconstructed fine time Parabolic fit Peak processor (one channel) Peak finder (one channel)

11. 01/04/09A. Salamon – TDAQ WG - CERN11 80 MHz sampling: 50 ps/bin full scale pulse -> 100 ps rms 40 MHz sampling: 100 ps/bin 1/40 full scale pulse + noise and jitter -> 700 ps rms simulation Some plots (digital simulation!!!)

12. 01/04/09A. Salamon – TDAQ WG - CERN12 Front-End PP FPGA multipliers, dividers: lot of Logic Elements Fmax ~ 80 MHz 80% device usage on an EP1S25

13. 01/04/09A. Salamon – TDAQ WG - CERN13 Front-End PP FPGA (new!!) multipliers, dividers: lot of Logic Elements RATE: 5 samples @ 80 MHz = 16 MHz / PP FPGA

14. 01/04/09A. Salamon – TDAQ WG - CERN14 Hit rates (Front-End TELL1s) Instantaneous design hit rate (Marco’s TDAQ note): 30 MHz Rate in the central region (Giuseppe’s private communication): 3 times mean hit rate Clusters of 256 liquid krypton cells (conservative) All hits generate a shower (conservative) ( 30 MHz / 28 ) x 3 = 3.2 ( 30 MHz / 28 ) x 3 / 8 = 0.4 TOTAL RATE = 10.8 MHz vs 64 bit/cluster over 3 gbit eth links

15. 01/04/09A. Salamon – TDAQ WG - CERN15 Hit rates (PP FPGA = ¼ TELL1) Same assumptions Fast communication between PP FPGAs in the same TELL1 -> rate reduction ( 30 MHz / 28 ) x 3 / 8 = 0.4 TOTAL RATE = 4.8 MHz vs 64 bit/cluster over 32b @ 160 MHz ( 30 MHz / 28 ) x 3 /4 = 0.8

16. 01/04/09A. Salamon – TDAQ WG - CERN16 Concentrator TELL1 (overlkap handling and hit rates) Maximum in the red area: the cluster is handled by the “red” TELL1 concentrator Maximum in the blue area: the cluster is handled by the “blue” TELL1 concentrator Double counting resolved at the level of the concentrator Only 4 over 8 Front-End TELL1s contribute to the output hit rate: OUTPUT RATE = (30 MHz / 28) x 3 x 4 = 12.9 MHz vs 64 bit/cluster over 3 gbit eth links

17. 01/04/09A. Salamon – TDAQ WG - CERN17 Lab tests: front-end We are preparing our test station for the Front-End mezzanine AWG 2021 -> mezzanino analog sums -> cable -> TELL1 analog mezzanine -> TELL1 Same signal in two different analog sums channels time resolution rms = sigma(T1-T2)/sqrt(2) Arbitrary waveform generator: AWG2021 NA48 analog sum card TELL1 TELL1 analog mezzanine

18. 01/04/09A. Salamon – TDAQ WG - CERN18 Lab tests: concentrator link We are also working at the test station for our receiver Use an altera development kit (Stratix II 60k Logic Elements) to validate and study the receiver ethernet

19. 01/04/09A. Salamon – TDAQ WG - CERN19 Time schedule End of april – beginning of may: FE and ethernet link tests in the lab Then start mezzanines desing Then try to test the system on the liquid krypton (with LHCb ADC mezzanine first)