1. Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ CprE 281: Digital Logic

2. Intro to Verilog CprE 281: Digital Logic Iowa State University, Ames, IA Copyright © Alexander Stoytchev

3. Administrative Stuff HW3 is due on Monday Sep 14 @ 4p

4. Administrative Stuff HW4 is out It is due on Monday Sep 21 @ 4pm. Please write clearly on the first page (in BLOCK CAPITAL letters) the following three things:  Your First and Last Name  Your Student ID Number  Your Lab Section Letter Also, please  Staple your pages  Use Letter-sized sheets

5. Administrative Stuff Midterm Exam #1 When: Friday Sep 25. Where: This classroom What: Chapter 1 and Chapter 2 plus number systems The exam will be open book and open notes (you can bring up to 3 pages of handwritten notes). More details to follow.

6. Quick Review

7. NAND followed by NOT = AND x1x1 x2x2 f 000 010 100 111 x 1 x 2 x 1 x 2  x1x1 x2x2 f 001 011 101 110 x 1 x 2  f 0 0 0 1 x 1 x 2 x 1 x 2 

8. DeMorgan’s Theorem

9. x x y y x + y = x y x y 

10. Sum-Of-Products x 1 x 2 x 3 x 4

11. x 1 x 2 x 3 x 4 AND AND OR

12. Sum-Of-Products x 1 x 2 x 3 x 4 AND AND OR x 1 x 2  x 1 x 2 x 1 x 2  x 3 x 4  x 3 x 4 x 3 x 4  x 1 x 2  x 3 x 4  +

13. Sum-Of-Products x 1 x 2 x 3 x 4 AND AND OR x 1 x 2  x 1 x 2 x 1 x 2  x 3 x 4  x 3 x 4 x 3 x 4  x 1 x 2  x 3 x 4  + AND AND OR

14. Sum-Of-Products x 1 x 2 x 3 x 4 AND AND OR x 1 x 2  x 1 x 2 x 1 x 2  x 3 x 4  x 3 x 4 x 3 x 4  x 1 x 2  x 3 x 4  +

15. Sum-Of-Products x 1 x 2 x 3 x 4 AND AND OR x 1 x 2  x 1 x 2 x 1 x 2  x 3 x 4  x 3 x 4 x 3 x 4  x 1 x 2  x 3 x 4  + NAND

16. Sum-Of-Products x 1 x 2 x 3 x 4 AND AND OR x 1 x 2 x 1 x 2  x 3 x 4 x 3 x 4  x 1 x 2  x 3 x 4  +

17. Sum-Of-Products x 1 x 2 x 3 x 4 x 5 x 1 x 2 x 3 x 4 x 5 x 1 x 2 x 3 x 4 x 5

18. 2-1 Multiplexer (Definition) Has two inputs: x 1 and x 2 Also has another input line s If s=0, then the output is equal to x 1 If s=1, then the output is equal to x 2

19. Graphical Symbol for a 2-1 Multiplexer f s x 1 x 2 0 1 [ Figure 2.33c from the textbook ]

20. Let’s Derive the SOP form s x 1 x 2 f (s, x 1, x 2 ) = s x 1 x 2 +++

21. Let’s simplify this expression f (s, x 1, x 2 ) = s x 1 x 2 +++ f (s, x 1, x 2 ) = s x 1 (x 2 + x 2 )s (x 1 +x 1 )x 2 ++ f (s, x 1, x 2 ) = s x 1 s x 2 +

22. Circuit for 2-1 Multiplexer f x 1 x 2 s f s x 1 x 2 0 1 (c) Graphical symbol (b) Circuit [ Figure 2.33b-c from the textbook ]

23. Analogy: Railroad Switch http://en.wikipedia.org/wiki/Railroad_switch]

24. Analogy: Railroad Switch http://en.wikipedia.org/wiki/Railroad_switch] select x1x1 x2x2 f

25. Analogy: Railroad Switch http://en.wikipedia.org/wiki/Railroad_switch] select x1x1 x2x2 f This is not a perfect analogy because the trains can go in either direction, while the multiplexer would only allow them to go from top to bottom.

26. More Compact Truth-Table Representation 0000 0010 0101 0111 1000 1011 1100 1111 (a)Truthtable sx1x1 x2x2 f (s, x 1, x 2 ) [ Figure 2.33 from the textbook ] 0 1 f (s, x 1, x 2 ) s x1x1 x2x2

27. 4-1 Multiplexer (Definition) Has four inputs: w 0, w 1, w 2, w 3 Also has two select lines: s 1 and s 0 If s 1 =0 and s 0 =0, then the output f is equal to w 0 If s 1 =0 and s 0 =1, then the output f is equal to w 1 If s 1 =1 and s 0 =0, then the output f is equal to w 2 If s 1 =1 and s 0 =1, then the output f is equal to w 3 We’ll talk more about this when we get to chapter 4, but here is a quick preview.

28. Graphical Symbol and Truth Table [ Figure 4.2a-b from the textbook ]

29. The long-form truth table [http://www.absoluteastronomy.com/topics/Multiplexer]

30. 4-1 Multiplexer (SOP circuit) [ Figure 4.2c from the textbook ]

31. 0 w 0 w 1 0 1 w 2 w 3 0 1 f 0 1 s 1 s Using three 2-to-1 multiplexers to build one 4-to-1 multiplexer [ Figure 4.3 from the textbook ]

32. Analogy: Railroad Switches http://en.wikipedia.org/wiki/Railroad_switch]

33. Analogy: Railroad Switches http://en.wikipedia.org/wiki/Railroad_switch] s1s1 w0w0 f w1w1 w2w2 w3w3

34. Analogy: Railroad Switches http://en.wikipedia.org/wiki/Railroad_switch] s1s1 w0w0 f w1w1 w2w2 w3w3 these two switches are controlled together s0s0

35. Using three 2-to-1 multiplexers to build one 4-to-1 multiplexer

36. Using three 2-to-1 multiplexers to build one 4-to-1 multiplexer f s1s1 s0s0 w0w0 w1w1 w2w2 w3w3

37. That is different from the SOP form of the 4-1 multiplexer shown below, which uses less gates

38. w 8 w 11 s 1 w 0 s 0 w 3 w 4 w 7 w 12 w 15 s 3 s 2 f 16-1 Multiplexer [ Figure 4.4 from the textbook ]

39. [http://upload.wikimedia.org/wikipedia/commons/2/26/SunsetTracksCrop.JPG]

40. 7-Segment Display Example

41. Display of numbers [ Figure 2.34 from the textbook ]

42. Display of numbers

43. b = 1 e = s 0 c = s 1 f = s 1 s 0 g = s 1 s 0 a = s 0 d = s 0

44. Intro to Verilog

45. History Created in 1983/1984 Verilog-95 (IEEE standard 1364-1995) Verilog 2001 (IEEE Standard 1364-2001) Verilog 2005 (IEEE Standard 1364-2005) SystemVerilog SystemVerilog 2009 (IEEE Standard 1800-2009).

46. HDL Hardware Description Language Verilog HDL VHDL

47. Verilog HDL != VHDL These are two different Languages! Verilog is closer to C VHDL is closer to Ada

48. [ Figure 2.35 from the textbook ]

49. “Hello World” in Verilog [http://en.wikipedia.org/wiki/Verilog]

50. x 1 x 2 x 1 x 2 + AND gate x x x 1 x 2 x 1 x 2  The Three Basic Logic Gates [ Figure 2.8 from the textbook ] OR gate NOT gate

51. How to specify a NOT gate in Verilog NOT gate xx

52. xy How to specify a NOT gate in Verilog NOT gate we’ll use the letter y for the output

53. xy How to specify a NOT gate in Verilog NOT gate not (y, x) Verilog code

54. How to specify an AND gate in Verilog AND gate and (f, x1, x2) Verilog code x 1 x 2 x 1 x 2  f=

55. How to specify an OR gate in Verilog OR gate or (f, x1, x2) Verilog code x 1 x 2 x 1 x 2 + f=

56. 2-1 Multiplexer [ Figure 2.36 from the textbook ]

57. Verilog Code for a 2-1 Multiplexer [ Figure 2.37 from the textbook ][ Figure 2.36 from the textbook ]

58. Verilog Code for a 2-1 Multiplexer [ Figure 2.40 from the textbook ][ Figure 2.36 from the textbook ]

59. Verilog Code for a 2-1 Multiplexer [ Figure 2.42 from the textbook ][ Figure 2.36 from the textbook ]

60. Verilog Code for a 2-1 Multiplexer [ Figure 2.43 from the textbook ][ Figure 2.36 from the textbook ]

61. Another Example

62. Let’s Write the Code for This Circuit [ Figure 2.39 from the textbook ]

63. [ Figure 2.38 from the textbook ] Let’s Write the Code for This Circuit module example2 (x1, x2, x3, x4, f, g, h); input x1, x2, x3, x4; output f, g, h; and (z1, x1, x3); and (z2, x2, x4); or (g, z1, z2); or (z3, x1, ~x3); or (z4, ~x2, x4); and (h, z3, z4); or (f, g, h); endmodule [ Figure 2.39 from the textbook ]

64. [ Figure 2.41 from the textbook ] Let’s Write the Code for This Circuit [ Figure 2.39 from the textbook ] module example4 (x1, x2, x3, x4, f, g, h); input x1, x2, x3, x4; output f, g, h; assign g = (x1 & x3) | (x2 & x4); assign h = (x1 | ~x3) & (~x2 | x4); assign f = g | h; endmodule

65. Yet Another Example

66. A logic circuit with two modules [ Figure 2.44 from the textbook ]

67. The adder module [ Figure 2.12 from the textbook ]

68. The adder module [ Figure 2.45 from the textbook ]

69. The display module b = 1 e = s 0 c = s 1 f = s 1 s 0 g = s 1 s 0 a = s 0 d = s 0

70. The display module b = 1 e = s 0 c = s 1 f = s 1 s 0 g = s 1 s 0 a = s 0 d = s 0 [ Figure 2.46 from the textbook ]

71. Putting it all together

72. Questions?

73. THE END